Pitfalls for transient response analysis with VF-TLP von Smedes, Theo, Coenen, Mart, Sluiter, Sander, Cappon, Paul

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Over-stress and under-stress effects in CDM testing von O'Sullivan, Greg, Smedes, Theo, Derikx, Richard, Garcia, Artemio, Knoppers, Bob

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High-Voltage ESD Protection Device With Fast Transient Reaction and High Holding Voltage von Lai, Da-Wei, de Raad, Gijs, Sque, Stephen, Peters, Wim, Smedes, Theo

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Gate-Lifted nMOS ESD Protection Device Triggered by a p-n-p in Series With a Diode von Lai, Da-Wei, Sque, Stephen, Peters, Wim, Smedes, Theo

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Bidirectional ESD Protection Device Using PNP With pMOS-Controlled Nwell Bias von Lai, Da-Wei, de Raad, Gijs, Tseng, Wei-Jhih, Smedes, Theo, Huitsing, Albert Jan

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CDM Simulation Based on Tester, Package and Full Integrated Circuit Modeling: Case Study von Abessolo-Bidzo, D., Smedes, T., Huitsing, A. J.

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On-chip system level protection of FM antenna pin with improved linearity von Notermans, Guido, Maksimovic, Dejan, Vermont, Gerd, Maasakkers, Michiel van, Pusa, Fredrik, Smedes, Theo

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An ESD test reduction method for complex devices von Maksimovic, Dejan, Blanc, Fabrice, Notermans, Guido, Smedes, Theo, Keller, Thomas

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ESD protection for thin gate oxides in 65nm von Notermans, Guido, Smedes, Theo, Mrčarica, Željko, Jong, Peter de, Stephan, Ralph, Zwol, Hans van, Maksimovic, Dejan

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ESD protection for thin gate oxides in 65 nm von Notermans, Guido, Smedes, Theo, Mrčarica, Željko, Jong, Peter de, Stephan, Ralph, Zwol, Hans van, Maksimovic, Dejan

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ESD robust high-voltage active clamps von Notermans, Guido, Quittard, Olivier, Heringa, Anco, Mrčarica, Željko, Blanc, Fabrice, Zwol, Hans van, Smedes, Theo, Keller, Thomas, Jong, Peter de

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An ESD test reduction method for complex devices : Electrostatic Discharge Reliability von MAKSIMOVIC, Dejan, BLANC, Fabrice, NOTERMANS, Guido, SMEDES, Theo, KELLER, Thomas

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C1. system level stress and the impact on device ESD protection von Smedes, Theo

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Role of package parasitics and substrate resistance on the Charged Device Model (CDM) failure levels –An explanation and die protection strategy von Sowariraj, M.S.B., Smedes, Theo, Salm, Cora, Mouthaan, Ton, Kuper, Fred G

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A 3-D Circuit Model to evaluate CDM performance of ICs von Sowariraj, M.S.B., Smedes, Theo, de Jong, Peter C., Salm, Cora, Mouthaan, Ton, Kuper, Fred G

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ESD robust high-voltage active clamps : Electrostatic Discharge Reliability von NOTERMANS, Guido, QUITTARD, Olivier, HERINGA, Anco, MRCARICA, Zeljko, BLANC, Fabrice, VAN ZWOL, Hans, SMEDES, Theo, KELLER, Thomas, DE JONG, Peter

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The influence of technology variation on ggNMOSTs and SCRs against CDM BSD stress von Sowariraj, M.S.B., Salm, Cora, Mouthaan, Ton, G Kuper, Fred, Smedes, Theo

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Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress von Sowariraj, M.S.B., de Jong, P.C., Cora, S.M., Smedes, T., Mouthaan, A.J.T., Kuper, F.G.

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HMM round robin study: What to expect when testing components to the IEC 61000-4-2 waveform von Muhonen, K., Ashton, R., Smedes, T., Scholz, M., Velghe, R., Barth, J., Peachey, N., Stadler, W., Grund, E.

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On-chip system level protection of FM antenna pin von Notermans, G, Maksimovic, D, Vermont, G, van Maasakkers, M, Pusa, F, Smedes, T

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