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  1. 1
    Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs

    Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs von LEIBOWITZ, MOSHE, SHWARTZBURD, VICTOR, BAR-DAVID, AYAL, AHARON, AHARON, GOFMAN, EMANUEL, GEWIRTZMAN,RAANAN

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  2. 2
    DYNAMIC PROCESS FOR THE GENERATION OF BIASED PSEUDO-RANDOM TEST PATTERNS FOR THE FUNCTIONAL VERIFICATION OF HARDWARE DESIGNS

    DYNAMIC PROCESS FOR THE GENERATION OF BIASED PSEUDO-RANDOM TEST PATTERNS FOR THE FUNCTIONAL VERIFICATION OF HARDWARE DESIGNS von AHARON, AHARON, BAR-DAVID, AYAL, LEIBOWITZ, MOSHE, SHWARTZBURD, VICTOR, GEWIRTZMAN, RAANAN, GOFMAN, EMANUEL

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  3. 3
    DYNAMIC PROCESS FOR THE GENERATION OF BIASED PSEUDO-RANDOM TEST PATTERNS FOR THE FUNCTIONAL VERIFICATION OF HARDWARE DESIGNS

    DYNAMIC PROCESS FOR THE GENERATION OF BIASED PSEUDO-RANDOM TEST PATTERNS FOR THE FUNCTIONAL VERIFICATION OF HARDWARE DESIGNS von LEIBOWITZ, MOSHE, BAR-DAVID, AYAL, AHARON, AHARON, GOFMAN, EMANUEL, SHWARTZBURD. VICTOR

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  4. 4
    Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs

    Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs von LEIBOWITZ, MOSHE, GEWIRTZMAN RAANAN, BAR-DAVID, AYAL, AHARON, AHARON, GOFMAN, EMANUEL, SHWARTZBURD. VICTOR

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