A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture von Kobayashi, T., Nogami, K., Shirotori, T., Fujimoto, Y.

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Thermal Shock Resistance of ZrO2-Toughened MgO von OKAMOTO, Takashi, IKUMA, Yasuro, SHIMAOKA, Mitsutaka, SHIROTORI, Tsukasa, KOMATSU, Wazo

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High speed output circuit having current driving capability which is independent of temperature and power supply voltage von SHIROTORI, TSUKASA

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LSI layout design apparatus, layout design method, recording medium recording layout design program, and semiconductor integrated circuit von Shirotori, Tsukasa, Urakawa, Yukihiro

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LSI layout design apparatus, layout design method, recording medium recording layout design program, and semiconductor integrated circuit von SHIROTORI TSUKASA, URAKAWA YUKIHIRO

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LSI layout design apparatus, layout design method, recording medium recording layout design program, and semiconductor integrated circuit von Urakawa, Yukihiro, Shirotori, Tsukasa

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LSI layout design apparatus, layout design method, recording medium recording layout design program, and semiconductor integrated circuit von SHIROTORI TSUKASA, URAKAWA YUKIHIRO

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Cache memory system having high and low speed and power consumption modes in which different ways are selectively enabled depending on a reference clock frequency von SHIROTORI, TSUKASA, HAYAKAWA, SHIGEYUKI

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Cache memory system with reduced tag memory power consumption von KAWASUMI, ATSUSHI, SHIROTORI, TSUKASA

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Semiconductor integrated circuit von NOGAMI, KAZUTAKA, SHIROTORI, TSUKASA

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Semiconductor integrated circuit capable of testing memory blocks von NOGAMI, KAZUTAKA, SHIROTORI, TSUKASA

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Semiconductor integrated circuit von NOGAMI, KAZUTAKA, SHIROTORI, TSUKASA

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Thermal Shock Resistance of ZrO2-Toughened MgO von OKAMOTO, Takashi, IKUMA, Yasuro, SHIMAOKA, Mitsutaka, SHIROTORI, Tsukasa, KOMATSU, Wazo

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A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC von Nogami, K., Sakurai, T., Sawada, K., Sakaue, K., Miyazawa, Y., Tanaka, S., Hiruta, Y., Katoh, K., Takayanagi, T., Shirotori, T., Itoh, Y., Uchida, M., Iizuka, T.

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A 32 kbyte integrated cache memory von Sawada, K., Sakurai, T., Nogami, K., Shirotori, T., Takayanagi, T., Iizuka, T., Maeda, T., Matsunaga, J., Fuji, H., Maeguchi, K., Kobayashi, K., Ando, T., Hayakashi, Y., Miyoshi, A., Sato, K.

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Halbleiteranordnung mit einer Logikschaltung und einem Speicher von SAWADA, KAZUHIRO, SAKURAI, TAKAYASU, SHIROTORI, TSUKASA

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Semiconductor device comprising a logic circuit and a memory von SAWADA, KAZUHIRO, SAKURAI, TAKAYASU, SHIROTORI, TSUKASA

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Semiconductor memory device employing sense amplifier control circuit and word line control circuit von NOGAMI, KAZUTAKA, SHIROTORI, TSUKASA, KOBAYASHI, TSUGUO

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A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode von Sawada, K., Sakurai, T., Nogami, K., Sato, K., Shirotori, T., Kakuma, M., Morita, S., Kinugawa, M., Asami, T., Narita, K., Matsunaga, J., Higuchi, A., Isobe, M., Iizuka, T.

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Semiconductor device von SAWADA, KAZUHIRO, SHIROTORI, TSUKASA, SAKURAI, TAKAYASU

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