The Next Generation 64b SPARC Core in a T4 SoC Processor von Shin, Jinuk Luke, Golla, Robert, Li, Hongping, Dash, Sudesna, Choi, Youngmoon, Smith, Alan, Sathianathan, Harikaran, Joshi, Mayur, Park, Heechoul, Elgebaly, Mohamed, Turullols, Sebastian, Kim, Song, Masleid, Robert, Konstadinidis, Georgios K., Doherty, Mary Jo, Grohoski, Greg, McAllister, Curtis

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A Power-Efficient High-Throughput 32-Thread SPARC Processor von Leon, A.S., Tam, K.W., Shin, J.L., Weisner, D., Schumacher, F.

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A 40 nm 16-Core 128-Thread SPARC SoC Processor von Shin, Jinuk Luke, Huang, Dawei, Petrick, Bruce, Hwang, Changku, Tam, Kenway W., Smith, Alan, Pham, Ha, Li, Hongping, Johnson, Timothy, Schumacher, Francis, Leon, Ana Sonia, Strong, Allan

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A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm von Hart, Jason M., Hoyeol Cho, Yuefei Ge, Gruber, Gregory, Dawei Huang, Changku Hwang, Jian, Daisy, Johnson, Tim, Konstadinidis, Georgios K., Krishnaswamy, Venkat, Kwong, Lance, Masleid, Robert P., Mehta, Rakesh, Nawathe, Umesh, Ramachandran, Aparna, Sathianathan, Hari, Yongning Sheng, Shin, Jinuk Luke, Turullols, Sebastian, Zuxu Qin, Yen, King C.

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A 40nm 16-core 128-thread CMT SPARC SoC processor von Shin, Jinuk Luke, Tam, Kenway, Huang, Dawei, Petrick, Bruce, Pham, Ha, Hwang, Changku, Li, Hongping, Smith, Alan, Johnson, Timothy, Schumacher, Francis, Greenhill, David, Leon, Ana Sonia, Strong, Allan

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Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference von Beigne, Edith, Shin, Jinuk Luke, Oike, Yusuke, Kim, Chulwoo, Genoe, Jan

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Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference von Beigne, Edith, Shin, Jinuk Luke, Oike, Yusuke, Kim, Chulwoo, Genoe, Jan

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The UltraSPARC T1 Processor: CMT Reliability von Leon, A.S., Langley, B., Jinuk Luke Shin

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A dual-core 64-bit ultraSPARC microprocessor for dense server applications von Takayanagi, T., Shin, J.L., Petrick, B., Su, J.Y., Levy, H., Ha Pham, Son, J., Moon, N., Bistry, D., Nair, U., Singh, M., Mathur, V., Leon, A.S.

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IC With Delay-Locked Loop With Widened Lock Range von SHIN, Jinuk, RAHMAN, Fahim ur

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Delay-locked loop with widened lock range von Shin, Jinuk, Rahman, Fahim Ur

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HIGH-BANDWIDTH POWER ESTIMATOR von ZHOU, Junwei, CHOI, Youngmoon, SHIN, Jinuk

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High-bandwidth power estimator for AI accelerator von Shin, Jinuk, Zhou, Junwei, Choi, Youngmoon

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Bandwidth and power management of glueless 8-socket SPARC T5 system von Krishnaswamy, V., Dawei Huang, Turullols, S., Shin, J. L.

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Design and implementation of an embedded 512-KB level-2 cache subsystem von Shin, J.L., Petrick, B., Singh, M., Leon, A.S.

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Timing Margin Sensor von SARKAR, Satyajit, SHIN, Jinuk, KHAYATZADEH, Mahmood

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Delay-Locked Loop with Widened Lock Range von SHIN, Jinuk, RAHMAN, Fahim UR

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HIGH-BANDWIDTH POWER ESTIMATOR FOR AI ACCELERATOR von ZHOU, Junwei, CHOI, Youngmoon, SHIN, Jinuk

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HIGH-BANDWIDTH POWER ESTIMATOR FOR AI ACCELERATOR von ZHOU, Junwei, CHOI, Youngmoon, SHIN, Jinuk

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High-performance flip-flop von Shin, Jinuk, Pham, Ha, Otaguro, Yukio

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