Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices von Miki, Takuji, Nagata, Makoto, Sonoda, Hiroki, Miura, Noriyuki, Okidono, Takaaki, Araga, Yuuki, Watanabe, Naoya, Shimamoto, Haruo, Kikuchi, Katsuya

Volltext

Residual stress investigation of via-last through-silicon via by polarized Raman spectroscopy measurement and finite element simulation von Feng, Wei, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya

Volltext

Validation of TSV thermo-mechanical simulation by stress measurement von Feng, Wei, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya

Volltext

Fabrication and stress analysis of annular-trench-isolated TSV von Feng, Wei, Bui, Tung Thanh, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya

Volltext

Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer von Watanabe, Naoya, Kikuchi, Hidekazu, Yanagisawa, Azusa, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro, Nakamura, Akio

Volltext

Investigation of transient thermal dissipation in thinned LSI for advanced packaging von Araga, Yuuki, Shimamoto, Haruo, Melamed, Samson, Kikuchi, Katsuya, Aoyagi, Masahiro

Volltext

Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer von Watanabe, Naoya, Kikuchi, Hidekazu, Yanagisawa, Azusa, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro, Nakamura, Akio

Volltext

QFP/quartz Adhesive Bonding with Surface Treatment for Physical Security of Edge Artificial Intelligence Devices von Nodaka, Hiro, Tezuka, Ami, Kuwae, Hiroyuki, Yamada, Kosuke, Hoga, Morihisa, Shimamoto, Haruo, Shoji, Shuichi, Mizuno, Jun

Volltext

Effect of TEOS layer on wafer warpage for wafer-to-wafer bonding von Feng, Wei, Shimamoto, Haruo, Kikuchi, Katsuya

Volltext

Warpage Reduction and Thermal Stress Study of Dicing Process in Wafer-to-Wafer Bonding Fabrication von Feng, Wei, Shimamoto, Haruo, Kawagoe, Tsuyoshi, Honma, Ichirou, Yamasaki, Masato, Okutsu, Fumitake, Masuda, Takatoshi, Kikuchi, Katsuya

Volltext

Stress investigation of annular-trench-isolated TSV by polarized Raman spectroscopy measurement and finite element simulation von Feng, Wei, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya

Volltext

Wafer-to-Wafer Bonding Fabrication Process-Induced Wafer Warpage von Feng, Wei, Shimamoto, Haruo, Kawagoe, Tsuyoshi, Honma, Ichirou, Yamasaki, Masato, Okutsu, Fumitake, Masuda, Takatoshi, Kikuchi, Katsuya

Volltext

Material effect on thermal stress of annular-trench-isolated through silicon via (TSV) von Feng, Wei, Watanabe, Naoya, Shimamoto, Haruo, Aoyagi, Masahiro, Kikuchi, Katsuya

Volltext

3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance von Monta, Kazuki, Sonoda, Hiroki, Okidono, Takaaki, Araga, Yuuki, Watanabe, Naoya, Shimamoto, Haruo, Kikuchi, Katsuya, Miura, Noriyuki, Miki, Takuji, Nagata, Makoto

Volltext

Study of wafer warpage reduction by dicing street von Feng, Wei, Shimamoto, Haruo, Kawagoe, Tsuyoshi, Honma, Ichirou, Yamasaki, Masato, Okutsu, Fumitake, Masuda, Takatoshi, Kikuchi, Katsuya

Volltext

A Thick Cu Layer Buried in Si Interposer Backside for Global Power Routing von Araga, Yuuki, Nagata, Makoto, Ikeda, Hiroaki, Miki, Takuji, Miura, Noriyuki, Watanabe, Naoya, Shimamoto, Haruo, Kikuchi, Katsuya

Volltext

TSV Bottom Cleaning Process for High Yield Formation of Via-Last TSVs von Watanabe, Naoya, Kikuchi, Kikuchi, Yanagisawa, Azusa, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro, Nakamura, Akio

Volltext

Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits von Melamed, Samson, Watanabe, Naoya, Nemoto, Shunsuke, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro

Volltext

Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits von Melamed, Samson, Watanabe, Naoya, Nemoto, Shunsuke, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro

Volltext

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging von Sonoda, Hiroki, Kasai, Ryo, Tanaka, Daisuke, Murakami, Yoshihide, Mihara, Kyoshi, Araga, Yuuki, Watanabe, Naoya, Shimamoto, Haruo, Kikuchi, Katsuya, Miki, Takuji, Nagata, Makoto

Volltext