WRAP-AROUND CONTACTS FOR FINFET AND TRI-GATE DEVICES FET von CEA, Stephen M. SM, MEHANDRU, Rishabh R, KUHN, Kelin K, SHIFREN, Lucian L

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A 90-nm logic technology featuring strained-silicon von Thompson, S.E., Armstrong, M., Auth, C., Alavi, M., Buehler, M., Chau, R., Cea, S., Ghani, T., Glass, G., Hoffman, T., Jan, C.-H., Kenyon, C., Klaus, J., Kuhn, K., Zhiyong Ma, Mcintyre, B., Mistry, K., Murthy, A., Obradovic, B., Nagisetty, R., Phi Nguyen, Sivakumar, S., Shaheed, R., Shifren, L., Tufts, B., Tyagi, S., Bohr, M., El-Mansy, Y.

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A logic nanotechnology featuring strained-silicon von Thompson, S.E., Armstrong, M., Auth, C., Cea, S., Chau, R., Glass, G., Hoffman, T., Klaus, J., Zhiyong Ma, Mcintyre, B., Murthy, A., Obradovic, B., Shifren, L., Sivakumar, S., Tyagi, S., Ghani, T., Mistry, K., Bohr, M., El-Mansy, Y.

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Physics of Hole Transport in Strained Silicon MOSFET Inversion Layers von Wang, E.X., Matagne, P., Shifren, L., Obradovic, B., Kotlyar, R., Cea, S., Stettler, M., Giles, M.D.

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Predictive Simulation and Benchmarking of Si and Ge pMOS FinFETs for Future CMOS Technology von Shifren, Lucian, Aitken, Robert, Brown, Andrew R., Chandra, Vikas, Binjie Cheng, Riddet, Craig, Alexander, Craig L., Cline, Brian, Millar, Campbell, Sinha, Saurabh, Yeric, Greg, Asenov, Asen

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Physical Modeling of Layout-Dependent Transistor Performance von Knutson, Karson L., Cea, Stephan, Giles, Martin, Keys, Patrick, Davids, Paul, Weber, Cory, Shifren, Lucian, Kotlyar, Roza, Hwang, Jack, Talukdar, Suddha, Stettler, Mark

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Strain Modeling in Advanced MOSFET Devices von Cea, Stephen, Ghani, Tahir, Giles, Martin, Kotlyar, Roza, Matagne, Philippe, Mistry, Kaizad, Obradovic, Borna, Shaheed, Reaz, Shifren, Lucian, Stettler, Mark, Tyagi, Sunit, Wang, Xiaoling, Weber, Cory, Keys, Patrick

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Physical Modeling of Layout-Dependent Transistor Performance von Knutson, Karson L., Cea, Stephan, Giles, Martin, Keys, Patrick, Davids, Paul, Weber, Cory, Shifren, Lucian, Kotlyar, Roza, Hwang, Jack, Talukdar, Suddha, Stettler, Mark

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Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress von BRASK JUSTIN K, DATTA SUMAN, METZ MATTHEW V, DOCZY MARK L, STETTLER MARK, DOYLE BRIAN S, SHIFREN LUCIAN, JIN BEEN Y, WANG EVERETT X, GILES MARTIN D, CHAU ROBERT S, MATAGNE PHILIPPE, KAVALIEROS JACK

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Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress von Kavalieros, Jack, Brask, Justin K, Doczy, Mark L, Metz, Matthew V, Datta, Suman, Doyle, Brian S, Chau, Robert S, Wang, Everett X, Matagne, Philippe, Shifren, Lucian, Jin, Been Y, Stettler, Mark, Giles, Martin D

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Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress von BRASK JUSTIN K, DATTA SUMAN, METZ MATTHEW V, DOCZY MARK L, STETTLER MARK, DOYLE BRIAN S, SHIFREN LUCIAN, JIN BEEN Y, WANG EVERETT X, GILES MARTIN D, CHAU ROBERT S, MATAGNE PHILIPPE, KAVALIEROS JACK

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Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress von BRASK JUSTIN K, DATTA SUMAN, METZ MATTHEW V, DOCZY MARK L, STETTLER MARK, DOYLE BRIAN S, SHIFREN LUCIAN, JIN BEEN Y, WANG EVERETT X, GILES MARTIN D, CHAU ROBERT S, MATAGNE PHILIPPE, KAVALIEROS JACK

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