Time-predictable architectures von Rochange, Christine, Sainrat, Pascal, Uhrig , Sascha

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MINOTAuR: A Timing Predictable RISC-V Core Featuring Speculative Execution von Gruin, Alban, Carle, Thomas, Rochange, Christine, Casse, Hugues, Sainrat, Pascal

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Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability von Ungerer, T, Cazorla, Francisco J, Sainrat, P, Bernat, G, Petrov, Z, Rochange, C, Quiñones, Eduardo, Gerdes, M, Paolieri, M, Wolf, J, Cassé, Hugues, Uhrig, S, Guliashvili, I, Houston, M, Kluge, F, Metzlaff, S, Mische, Jörg

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OTAWA: An Open Toolbox for Adaptive WCET Analysis von Ballabriga, Clément, Cassé, Hugues, Rochange, Christine, Sainrat, Pascal

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A Context-Parameterized Model for Static Analysis of Execution Times von Rochange, Christine, Sainrat, Pascal

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Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore von Ungerer, Theo, Bradatsch, Christian, Frieb, Martin, Kluge, Florian, Mische, Jörg, Stegmeier, Alexander, Jahr, Ralf, Gerdes, Mike, Zaykov, Pavel, Matusova, Lucie, Li, Zai Jian Jia, Petrov, Zlatko, Böddeker, Bert, Kehr, Sebastian, Regler, Hans, Hugl, Andreas, Rochange, Christine, Ozaktas, Haluk, Cassé, Hugues, Bonenfant, Armelle, Sainrat, Pascal, Lay, Nick, George, David, Broster, Ian, Quiñones, Eduardo, Panic, Milos, Abella, Jaume, Hernandez, Carles, Cazorla, Francisco, Uhrig, Sascha, Rohde, Mathias, Pyka, Arthur

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Time analysable synchronisation techniques for parallelised hard real-time applications von Gerdes, M., Kluge, F., Ungerer, T., Rochange, C., Sainrat, P.

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Time analysable synchronisation techniques for parallelised hard real-time applications von Gerdes, Mike, Kluge, Florian, Ungerer, Theo, Rochange, Christine, Sainrat, Pascal

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Predictable bus arbitration schemes for heterogeneous time-critical workloads running on multicore processors von Bourgade, R., Rochange, C., Sainrat, P.

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RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor von Wolf, Julian, Gerdes, Mike, Kluge, Florian, Uhrig, Sascha, Mische, Jörg, Metzlaff, Stefan, Rochange, Christine, Cassé, Hugues, Sainrat, Pascal, Ungerer, Theo

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Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets von Bourgade, Roman, Rochange, Christine, Sainrat, Pascal

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A Predictable Simultaneous Multithreading Scheme for Hard Real-Time von Barre, Jonathan, Rochange, Christine, Sainrat, Pascal

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Performance of M3S for the SOR algorithm von Rochange, Christine, Sainrat, Pascal, Litaize, Daniel

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Mastering the behavior of multi-core systems to match avionics requirements von Agrou, H., Sainrat, P., Gatti, M., Toillon, P.

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MBBA: A Multi-Bandwidth Bus Arbiter for Hard Real-Time von Bourgade, Roman, Rochange, Christine, De Michiel, Marianne, Sainrat, Pascal

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Example Architectures von Sainrat, Pascal, Uhrig , Sascha, Rochange, Christine

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Current Processor Architectures von Sainrat, Pascal, Uhrig , Sascha, Rochange, Christine

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Timing Analysis of Real-Time Systems von Sainrat, Pascal, Uhrig , Sascha, Rochange, Christine

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Real-Time Systems and Time Predictability von Sainrat, Pascal, Uhrig , Sascha, Rochange, Christine

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Memory Hierarchy von Sainrat, Pascal, Uhrig , Sascha, Rochange, Christine

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