High Throughput AES Algorithm Using Parallel Subbytes and MixColumn von Sridevi Sathya Priya, S., KarthigaiKumar, P., Sivamangai, N. M., Rejula, V.

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A Comparative Analysis of CNN Architectures and Regularization Techniques for Breast Cancer Classification in Mammograms von Vijetha, Kamal J., Priya, Sridevi S. Sathya

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FPGA implementation of AES algorithm for high speed applications von Priya, S. Sridevi Sathya, Karthigaikumar, P., Teja, Narayana Ravi

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Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications von Naveenkumar, R., Sivamangai, N. M., Napolean, A., Priya, S. Sridevi Sathya

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Implementation of multiplier using Vedic mathematics von S., Sridevi Sathya Priya, Dinesh Kumar Reddy, Chalimadugu, Ranganath Reddy, Somsagar, Arul Murugan, C.

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Design of INV/BUFF Logic Locking For Enhancing the Hardware Security von Naveenkumar, R., Sivamangai, N. M., Napolean, A., Priya, S. Sridevi Sathya, Ashika, S. V.

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Efficient Implementation of Carry-Skip Adder Using CSMT Adder and PPA von Sridevi Sathya Priya, S., Poulraju, Benita, Benita, B., Karanatakam, Dharani

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Split Ring Resonator-based Conformal Antenna for Earth Coverage Spaceborne Applications von Let, G. Shine, Nesasudha, M., Sivamangai, N. M., Priya, S. Sridevi Sathya

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FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications von Arul Murugan, C., Karthigaikumar, P., Sathya Priya, Sridevi

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An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box von Priya, Sridevi Sathya, Karthigaikumar, Palanivel, Siva Mangai, N. M., Kirti Gaurav Das, P.

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A highly secure cryptosystem for image encryption von Mitter, Rithmi, Priya, M. Sridevi Sathya

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A non linear equation based cryptosystem for image encryption and decryption von Mitter, R., Priya, M. Sridevi Sathya

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A high performance reconfigurable RSA processor von Kingston, O., Priya, S. S.

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