A Dual-Mode In-Memory Computing Unit Using Spin Hall-Assisted MRAM for Data-Intensive Applications von Monga, Kanika, Chaturvedi, Nitin, Gurunarayanan, S.

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Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders von Vendhan, Aalelai, Ahmed, Syed Ershad, Gurunarayanan, S.

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Design of a STT-MTJ Based Random-Access Memory With In-situ Processing for Data-Intensive Applications von Monga, Kanika, Chaturvedi, Nitin, Gurunarayanan, S.

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An optimal delay aware task assignment scheme for wireless SDN networked edge cloudlets von G., S.S. Chalapathi, Chamola, Vinay, Tham, Chen-Khong, S., Gurunarayanan, Ansari, Nirwan

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Energy-efficient data retention in D flip-flops using STT-MTJ von Monga, Kanika, Chaturvedi, Nitin, Gurunarayanan, S

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Design of a tunable delay line with on-chip calibration to generate process-invariant PWM signal for in-memory computing von Monga, Kanika, Shenoy, Meetha V., Chaturvedi, Nitin, Gurunarayanan, S.

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E-SATS: An Efficient and Simple Time Synchronization Protocol for Cluster- Based Wireless Sensor Networks von Chalapathi, G. S. S., Chamola, Vinay, Gurunarayanan, S., Sikdar, Biplab

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A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications von Kanika, Prasad, R. Sankara, Chaturvedi, Nitin, Gurunarayanan, S.

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Integrated Cooperative Synchronization for Wireless Sensor Networks von Chalapathi, G. S. S., Etzlinger, Bernhard, Gurunarayanan, S., Springer, Andreas

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An efficient adaptive block pinning for multicore architectures von Chaturvedi, Nitin, Gurunarayanan, S.

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An exploration of neuromorphic systems and related design issues/challenges in dark silicon era von Chandaliya, Mudit, Chaturvedi, Nitin, Gurunarayanan, S

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A testbed validated simple time synchronization protocol for clustered wireless sensor networks for IoT von Chalapathi, G.S.S., Chamola, Vinay, Gurunarayanan, S.

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Study of Various Factors Affecting Performance of Multi-Core Processors von Chaturvedi, Nitin, S, Gurunarayanan

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Register Allocation For Fine Grain Threads On Multicore Processor von Kiran, D. C, Gurunarayanan, S, Misra, Janardan P, Bhatia, Munish

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Global Scheduling Heuristics for Multicore Architecture von Nawal, Abhijeet, Misra, Janardan Prasad, Gurunarayanan, S., Kiran, D. C.

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A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling von Raveendran, Biju, Balasubramaniam, Sundar, Prasad, K Durga, Gurunarayanan, S.

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A Review of Deep Learning Techniques of Chest X-ray Analysis for Thoracic Disorders von Sharma, Pawan, Gurunarayanan, S., Karuppiah, Anupama

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Plasmonic Devices Electrically Driven by Tunnel Junctions von Gurunarayanan, S

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An adaptive migration–replication scheme (AMR) for shared cache in chip multiprocessors von Chaturvedi, Nitin, Subramaniyan, Arun, Gurunarayanan, S.

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Selective Cache Line Replication Scheme in Shared Last Level Cache von Chaturvedi, Nitin, Subramaniyan, Arun, Gurunarayanan, S.

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