Thread-Sensitive Instruction Issue for SMT Processors von Robatmili, B., Yazdani, N., Sardashti, S., Nourani, M.

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HASIL: hardware assisted software-based IP lookup for large routing tables von Mohammadi, H., Yazdani, N., Robatmili, B., Nourani, M.

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How to implement effective prediction and forwarding for fusable dynamic multicore architectures von Robatmili, B., Dong Li, Esmaeilzadeh, H., Govindan, S., Smith, A., Putnam, A., Burger, D., Keckler, S. W.

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Exploiting criticality to reduce bottlenecks in distributed uniprocessors von Robatmili, B, Govindan, S, Burger, D, Keckler, S W

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Strategies for mapping dataflow blocks to distributed hardware von Robatmili, Behnam, Coons, Katherine E., Burger, Doug, McKinley, Kathryn S.

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Optimizing SMT processors for IP-packet processing von Robatmili, Behnam, Yazdani, Nasser, Nourani, Mehrdad

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Augmenting general purpose processors for network processing von Ghasemi, H.R., Mohammadi, H., Robatmili, B., Yazdani, N.

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