Efficient Boolean Methods for Preparing Uniform Quantum States von Mozafari, Fereshte, Riener, Heinz, Soeken, Mathias, De Micheli, Giovanni

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Path-Based Program Repair von Riener, Heinz, Ehlers, Rüdiger, Fey, Görschwin

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Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron von Lee, Siang-Yun, Calvino, Alessandro Tempia, Riener, Heinz, Micheli, Giovanni De

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Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits von Rai, Shubham, Calvino, Alessandro Tempia, Riener, Heinz, De Micheli, Giovanni, Kumar, Akash

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Three-Input Gates for Logic Synthesis von Marakkalage, Dewmini Sudara, Testa, Eleonora, Riener, Heinz, Mishchenko, Alan, Soeken, Mathias, De Micheli, Giovanni

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Boolean satisfiability in quantum compilation von Soeken, Mathias, Meuli, Giulia, Schmitt, Bruno, Mozafari, Fereshte, Riener, Heinz, De Micheli, Giovanni

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A Simulation-Guided Paradigm for Logic Synthesis and Verification von Lee, Siang-Yun, Riener, Heinz, Mishchenko, Alan, Brayton, Robert K., De Micheli, Giovanni

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Boolean satisfiability in quantum compilation von Soeken, Mathias, Meuli, Giulia, Schmitt, Bruno, Mozafari, Fereshte, Riener, Heinz, De Micheli, Giovanni

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Synthesizing adaptive test strategies from temporal logic specifications von Bloem, Roderick, Fey, Goerschwin, Greif, Fabian, Könighofer, Robert, Pill, Ingo, Riener, Heinz, Röck, Franz

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metaSMT: focus on your application and not on solver integration von Riener, Heinz, Haedicke, Finn, Frehse, Stefan, Soeken, Mathias, Große, Daniel, Drechsler, Rolf, Fey, Goerschwin

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Evaluating ESOP Optimization Methods in Quantum Compilation Flows von Meuli, Giulia, Schmitt, Bruno, Ehlers, Rüdiger, Riener, Heinz, De Micheli, Giovanni

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FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation von Riener, Heinz, Fey, Görschwin

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Improving fault tolerance utilizing hardware-software-co-synthesis von Riener, Heinz, Frehse, Stefan, Fey, Gorschwin

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An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications von Lee, Siang-Yun, Riener, Heinz, De Micheli, Giovanni

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Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits von Lee, Siang-Yun, Riener, Heinz, De Micheli, Giovanni

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Safety Synthesis Sans Specification von Bloem, Roderick, Chockler, Hana, Ebrahimi, Masoud, Fisman, Dana, Riener, Heinz

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Simulation-Guided Boolean Resubstitution von Lee, Siang-Yun, Riener, Heinz, Mishchenko, Alan, Brayton, Robert K, De Micheli, Giovanni

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Exact Synthesis of ESOP Forms von Riener, Heinz, Ehlers, Rüdiger, Schmitt, Bruno, De Micheli, Giovanni

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An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications von Siang-Yun, Lee, Riener, Heinz, De Micheli, Giovanni

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Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits von Siang-Yun, Lee, Riener, Heinz, De Micheli, Giovanni

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