Deterministic Frequency and Voltage Enhancements on the POWER10 Processor von Vanderpool, Brian, Restle, Phillip J., Fluhr, Eric, Still, Gregory, Campisano, Francesco A., Charmichael, Ian, Marz, Eric, Batra, Rahul, Willaman, Richard

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Subtractive Router for Tree-Driven-Grid Clocks von Haifeng Qian, Restle, P. J., Kozhaya, J. N., Gunion, C. L.

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A Resonant Global Clock Distribution for the Cell Broadband Engine Processor von Chan, S.C., Restle, P.J., Bucelot, T.J., Liberty, J.S., Weitzel, S., Keaty, J.M., Flachs, B., Volant, R., Kapusta, P., Zimmerman, J.S.

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IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems von Berry, Christopher, Wolpert, David, Vezrytzis, Christos, Rizzolo, Richard, Carey, Sean, Maroz, Yaniv, Shi, Hunter, Chidambarrao, Dureseti, Jacobi, Christian, Saporito, Anthony, Strach, Thomas, Buyuktosunoglu, Alper, Lobo, Preetham, Chuang, Pierce, Owczarczyk, Pawel, Bertran, Ramon, Webel, Tobias, Restle, Phillip J.

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POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor von Wendel, D F, Kalla, R, Warnock, J, Cargnoni, R, Chu, S G, Clabes, J G, Dreps, D, Hrusecky, D, Friedrich, J, Islam, S, Kahle, J, Leenstra, J, Mittal, G, Paredes, J, Pille, J, Restle, P J, Sinharoy, B, Smith, G, Starke, W J, Taylor, S, Van Norstrand, J, Weitzel, S, Williams, P G, Zyuban, V

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Uniform-phase uniform-amplitude resonant-load global clock distributions von Chan, S.C., Shepard, K.L., Restle, P.J.

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Distributed Differential Oscillators for Global Clock Networks von Chan, S.C., Shepard, K.L., Restle, P.J.

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A clock distribution network for microprocessors von Restle, P.J., McNamara, T.G., Webber, D.A., Camporese, P.J., Eng, K.F., Jenkins, K.A., Allen, D.H., Rohn, M.J., Quaranta, M.P., Boerstler, D.W., Alpert, C.J., Carter, C.A., Bailey, R.N., Petrovick, J.G., Krauter, B.L., McCredie, B.D.

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When are transmission-line effects important for on-chip interconnections? von Deutsch, A., Kopcsay, G.V., Restle, P.J., Smith, H.H., Katopis, G., Becker, W.D., Coteus, P.W., Surovic, C.W., Rubin, B.J., Dunne, R.P., Gallo, T., Jenkins, K.A., Terman, L.M., Dennard, R.H., Sai-Halasz, G.A., Krauter, B.L., Knebel, D.R.

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The clock distribution of the POWER4 microprocessor von Restle, P.J., Carter, C.A., Eckhardt, J.P., Krauter, B.L., McCredie, B.D., Jenkins, K.A., Weger, A.J., Mule, A.V.

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Full-wave PEEC time-domain method for the modeling of on-chip interconnects von Restle, P.J., Ruehli, A.E., Walker, S.G., Papadopoulos, G.

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SiGe-channel heterojunction p-MOSFET's von Verdonckt-Vandebroek, S., Crabbe, E.F., Meyerson, B.S., Harame, D.L., Restle, P.J., Stork, J.M.C., Johnson, J.B.

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Physical design of a fourth-generation POWER GHz microprocessor von Anderson, C.J., Petrovick, J., Keaty, J.M., Warnock, J., Nussbaum, G., Tendier, J.M., Carter, C., Chu, S., Clabes, J., DiLullo, J., Dudley, P., Harvey, P., Krauter, B., LeBlanc, J., Pong-Fei Lu, McCredie, B., Plum, G., Restle, P.J., Runyon, S., Scheuermann, M., Schmidt, S., Wagoner, J., Weiss, R., Weitzel, S., Zoric, B.

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Technical visualizations in VLSI design: visualization von Restle, Phillip J.

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A new 'shift and ratio' method for MOSFET channel-length extraction von Taur, Y., Zicherman, D.S., Lombardi, D.R., Restle, P.J., Hsu, C.H., Nanafi, H.I., Wordeman, M.R., Davari, B., Shahidi, G.G.

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1.1 to 1.6GHz distributed differential oscillator global clock network von Chan, S.C., Shepard, K.L., Restle, P.J.

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A 4.6GHz resonant global clock distribution network von Chan, S.C., Restle, P.J., Shepard, K.L., James, N.K., Franch, R.L.

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Interconnect in high speed designs: problems, methodologies and tools von Restle, Phillip J., Phillips, Joel, Elfadel, Ibrahim

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Mitigation of on-chip supply voltage noise by monitoring slope of supply voltage based on time-based sensors von Restle, Phillip J, Pathak, Divya, Vezyrtzis, Christos, Chuang, Pierce I

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Mitigation of on-chip supply voltage based on local and non-local (neighboring) cores' supply voltage information and decision von Restle, Phillip J, Vezyrtzis, Christos, Chuang, Pierce I

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