A clock distribution network for microprocessors von Restle, P.J., McNamara, T.G., Webber, D.A., Camporese, P.J., Eng, K.F., Jenkins, K.A., Allen, D.H., Rohn, M.J., Quaranta, M.P., Boerstler, D.W., Alpert, C.J., Carter, C.A., Bailey, R.N., Petrovick, J.G., Krauter, B.L., McCredie, B.D.

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Distributed Differential Oscillators for Global Clock Networks von Chan, S.C., Shepard, K.L., Restle, P.J.

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Uniform-phase uniform-amplitude resonant-load global clock distributions von Chan, S.C., Shepard, K.L., Restle, P.J.

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A Resonant Global Clock Distribution for the Cell Broadband Engine Processor von Chan, S.C., Restle, P.J., Bucelot, T.J., Liberty, J.S., Weitzel, S., Keaty, J.M., Flachs, B., Volant, R., Kapusta, P., Zimmerman, J.S.

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When are transmission-line effects important for on-chip interconnections? von Deutsch, A., Kopcsay, G.V., Restle, P.J., Smith, H.H., Katopis, G., Becker, W.D., Coteus, P.W., Surovic, C.W., Rubin, B.J., Dunne, R.P., Gallo, T., Jenkins, K.A., Terman, L.M., Dennard, R.H., Sai-Halasz, G.A., Krauter, B.L., Knebel, D.R.

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Full-wave PEEC time-domain method for the modeling of on-chip interconnects von Restle, P.J., Ruehli, A.E., Walker, S.G., Papadopoulos, G.

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Physical design of a fourth-generation POWER GHz microprocessor von Anderson, C.J., Petrovick, J., Keaty, J.M., Warnock, J., Nussbaum, G., Tendier, J.M., Carter, C., Chu, S., Clabes, J., DiLullo, J., Dudley, P., Harvey, P., Krauter, B., LeBlanc, J., Pong-Fei Lu, McCredie, B., Plum, G., Restle, P.J., Runyon, S., Scheuermann, M., Schmidt, S., Wagoner, J., Weiss, R., Weitzel, S., Zoric, B.

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A new 'shift and ratio' method for MOSFET channel-length extraction von Taur, Y., Zicherman, D.S., Lombardi, D.R., Restle, P.J., Hsu, C.H., Nanafi, H.I., Wordeman, M.R., Davari, B., Shahidi, G.G.

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SiGe-channel heterojunction p-MOSFET's von Verdonckt-Vandebroek, S., Crabbe, E.F., Meyerson, B.S., Harame, D.L., Restle, P.J., Stork, J.M.C., Johnson, J.B.

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Uniform-phase uniform-amplitude resonant-load global clock distributions von Chan, S C, Shepard, K L, Restle, P J

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Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor von Restle, P.J., Jenkins, K.A., Deutsch, A., Cook, P.W.

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1.1 to 1.6GHz distributed differential oscillator global clock network von Chan, S.C., Shepard, K.L., Restle, P.J.

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Technical visualizations in VLSI design von Restle, P.J.

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A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor von Thomson, M.G.R., Restle, P.J., James, N.K.

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A 4.6GHz resonant global clock distribution network von Chan, S.C., Restle, P.J., Shepard, K.L., James, N.K., Franch, R.L.

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A 400-MHz S/390 microprocessor von Webb, C.F., Anderson, C.J., Sigal, L., Shepard, K.L., Liptay, J.S., Warnock, J.D., Curran, B., Krumm, B.W., Mayo, M.D., Camporese, P.J., Schwarz, E.M., Farrell, M.S., Restle, P.J., Averill, R.M., Slegel, T.J., Houtt, W.V., Chan, Y.H., Wile, B., Nguyen, T.N., Emma, P.G., Beece, D.K., Ching-Te Chuang, Price, C.

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Timing uncertainty measurements on the Power5 microprocessor von Restle, P.J., Franch, R.L., James, N.K., Huott, W.V., Skergan, T.M., Wilson, S.C., Schwartz, N.S., Clabes, J.G.

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The clock distribution of the POWER4 microprocessor von Restle, P.J., Carter, C.A., Eckhardt, J.P., Krauter, B.L., McCredie, B.D., Jenkins, K.A., Weger, A.J., Mule, A.V.

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Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's von Sai-Halasz, G.A., Wordeman, M.R., Kern, D.P., Ganin, E., Rishton, S., Zicherman, D.S., Schmid, H., Polcari, M.R., Ng, H.Y., Restle, P.J., Chang, T.H.P., Dennard, R.H.

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Designing the best clock distribution network von Restle, P.J., Deutsch, A.

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