Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks von Sisejkovic, Dominik, Merchant, Farhad, Reimann, Lennart M., Leupers, Rainer

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Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach von Sisejkovic, Dominik, Merchant, Farhad, Reimann, Lennart M., Srivastava, Harshit, Hallawa, Ahmed, Leupers, Rainer

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Scaling Logic Locking Schemes to Multi-module Hardware Designs von Šišejković, Dominik, Merchant, Farhad, Reimann, Lennart M., Leupers, Rainer, Kegreiß, Sascha

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Automated Information Flow Analysis for Integrated Computing-in-Memory Modules von Reimann, Lennart M, Staudigl, Felix, Leupers, Rainer

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Quantitative Information Flow for Hardware: Advancing the Attack Landscape von Reimann, Lennart M, Erdönmez, Sarp, Sisejkovic, Dominik, Leupers, Rainer

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QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL von Reimann, Lennart M, Prashar, Anshul, Ghinami, Chiara, Pelke, Rebecca, Sisejkovic, Dominik, Merchant, Farhad, Leupers, Rainer

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Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction von Reimann, Lennart M, Yadu Madhukumar Variyar, Huelser, Lennet, Ghinami, Chiara, Germek, Dominik, Leupers, Rainer

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SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors von Reimann, Lennart M, Wiesner, Jonathan, Sisejkovic, Dominik, Merchant, Farhad, Leupers, Rainer

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Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks von Sisejkovic, Dominik, Merchant, Farhad, Reimann, Lennart M, Leupers, Rainer

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Automated Information Flow Analysis for Integrated Computing-in-Memory Modules von Reimann, Lennart M, Staudigl, Felix, Leupers, Rainer

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QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog von Reimann, Lennart M, Hanel, Luca, Sisejkovic, Dominik, Merchant, Farhad, Leupers, Rainer

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Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities von Sisejkovic, Dominik, Reimann, Lennart M, Moussavi, Elmira, Merchant, Farhad, Leupers, Rainer

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ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework von Merchant, Farhad, Sisejkovic, Dominik, Reimann, Lennart M, Yasotharan, Kirthihan, Grass, Thomas, Leupers, Rainer

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Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach von Sisejkovic, Dominik, Merchant, Farhad, Reimann, Lennart M, Srivastava, Harshit, Hallawa, Ahmed, Leupers, Rainer

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Quantitative Information Flow for Hardware: Advancing the Attack Landscape von Reimann, Lennart M, Erdönmez, Sarp, Sisejkovic, Dominik, Leupers, Rainer

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QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL von Reimann, Lennart M, Prashar, Anshul, Ghinami, Chiara, Pelke, Rebecca, Sisejkovic, Dominik, Merchant, Farhad, Leupers, Rainer

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SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors von Reimann, Lennart M, Wiesner, Jonathan, Sisejkovic, Dominik, Merchant, Farhad, Leupers, Rainer

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ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework von Merchant, Farhad, Sisejkovic, Dominik, Reimann, Lennart M, Yasotharan, Kirthihan, Grass, Thomas, Leupers, Rainer

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