A novel multiple species ringdown spectrometer for in situ measurements of methane, carbon dioxide, and carbon isotope von Wang, C., Srivastava, N., Jones, B.A., Reese, R.B.

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Paired T-element design for multiple-state acknowledge dependency von Taylor, R.A, Reese, R.B

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Cooperative and progressive design experience for embedded systems von Bruce, J.W., Harden, J.C., Reese, R.B.

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Paired T-element design for multiple-state acknowledge dependency von Taylor, R A, Reese, R B

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Early evaluation for performance enhancement in phased logic von Reese, R.B., Thornton, M.A., Traver, C., Hemmendinger, D.

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PLFire: A Visualization Tool for Asynchronous Phased Logic Designs von Fazel, K., Thornton, M. A., Reese, R. B.

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A coarse-grain phased logic CPU von Reese, R.B., Thornton, M.A., Traver, C.

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Uncle - An RTL Approach to Asynchronous Design von Reese, R. B., Smith, S. C., Thornton, M. A.

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Two-phase micropipeline control wrapper with early evaluation von Reese, R.B., Thornton, M.A., Traver, C.

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Fast two-phase micropipeline control wrapper for standard cell implementation von Reese, R.B., Thornton, M.A., Traver, C.

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Asynchronous rate divider and multiplier designs for LEDR logic von Traver, C., Harden, J.C., Goodjohn, K., Reese, R.B.

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The External Rhinoplasty Approach for Rhinologic Surgery von Reese, Bradley R., Koltai, Peter J., Parnes, Steven M., Decker, John W.

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Generalized early evaluation in self-timed circuits von Thornton, M.A., Fazel, K., Reese, R.B., Traver, C.

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Asynchronous rate divider and multiplier designs for LEDR logic von Traver, C, Harden, J C, Goodjohn, K, Reese, R B

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Two-phase micropipeline control wrapper with early evaluation von Reese, R B, Thornton, M A, Traver, C

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Fast two-phase micropipeline control wrapper for standard cell implementation von Reese, R B, Thornton, M A, Traver, C

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PLFire: a visualization tool for asynchronous phased logic designs von Fazel, K., Thornton, M.A., Reese, R.B.

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A coarse-grain phased logic CPU von Reese, R.B., Thornton, M.A., Traver, C.

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Early evaluation for phased logic circuits using BDDS and MVL von Fazel, K., Thornton, M.A., Reese, R.B.

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Arithmetic logic circuits using self-timed bit level dataflow and early evaluation von Reese, R.B., Thornton, M.A., Traver, C.

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