Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test von Devanathan, V.R., Ravikumar, C.P., Kamakoti, V.

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A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test von Devanathan, V.R., Ravikumar, C.P., Kamakoti, V.

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Partial Gating Optimization for Power Reduction During Test Application von ElShoukry, M., Tehranipoor, M., Ravikumar, C.P.

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Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers von Ahmed, Nisar, Tehranipoor, Mohammad, Ravikumar, C. P., Butler, Kenneth M.

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A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer von Arasu, S.T., Ravikumar, C.P., Nandy, S.K.

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On-chip memory architecture exploration framework for DSP processor-based embedded system on chip von Kumar, T.S. Rajesh, Govindarajan, R., Ravikumar, C.P.

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Test Strategies for Low Power Devices von Ravikumar, C.P., Hirech, M., Wen, X.

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Conference Reports von Ravikumar, C.P., Nurmi, Jari

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Source-based delay-bounded multicasting in multimedia networks von Ravikumar, C.P., Bajpai, Rajneesh

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On Power-profiling and Pattern Generation for Power-safe Scan Tests von Devanathan, V.R., Ravikumar, C.P., Kamakoti, V.

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PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test von Devanathan, V.R., Ravikumar, C.P., Mehrotra, R., Kamakoti, V.

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Variation-Tolerant, Power-Safe Pattern Generation von Devanathan, V.R., Ravikumar, C.P., Kamakoti, V.

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At-speed transition fault testing with low speed scan enable von Ahmed, N., Ravikumar, C.P., Tehranipoor, M., Plusquellic, J.

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Layout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs von Kokrady, A., Ravikumar, C.P., Chandrachoodan, N.

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Memory Architecture Exploration Framework for Cache Based Embedded SOC von Kumar, T.S.R., Ravikumar, C.P., Govindarajan, R.

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Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms von Devanathan, V.R., Ravikumar, C.P., Kamakoti, V.

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Enhanced launch-off-capture transition fault testing von Ahmed, N., Tehranipoor, M., Ravikumar, C.P.

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Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models von Kokrady, A., Ravikumar, C.P., Chandrachoodan, N.

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MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip von Rajesh Kumar, T.S., Ravikumar, C.P., Govindarajan, R.

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Conference Reports von Subhasish, M., Novak, O., Kubatova, H., Al-Hashimi, B.M., Marinissen, E.J., Ravikumar, C.P.

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