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  1. 1
    A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration

    A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration von Nagi, Sumeet Singh, Rathore, Uneeb, Sahoo, Krutikesh, Ling, Tim, Iyer, Subramanian S., Markovic, Dejan


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  2. 2
    Reconfigurable digital signal processing (DSP) vector engine

    Reconfigurable digital signal processing (DSP) vector engine von Rathore, Uneeb Yaqub, Nagi, Sumeet Singh, Sheikh, Farhana, Weber, Scott Jeremy

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  3. 3
    RECONFIGURABLE DIGITAL SIGNAL PROCESSING (DSP) VECTOR ENGINE

    RECONFIGURABLE DIGITAL SIGNAL PROCESSING (DSP) VECTOR ENGINE von Rathore, Uneeb Yaqub, Nagi, Sumeet Singh, Sheikh, Farhana, Weber, Scott Jeremy

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  4. 4
    RECONFIGURABLE DIGITAL SIGNAL PROCESSING (DSP) VECTOR ENGINE

    RECONFIGURABLE DIGITAL SIGNAL PROCESSING (DSP) VECTOR ENGINE von Rathore, Uneeb Yaqub, Nagi, Sumeet Singh, Sheikh, Farhana, Weber, Scott Jeremy

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  5. 5
    RECONFIGURABLE DIGITAL SIGNAL PROCESSING (DSP) VECTOR ENGINE

    RECONFIGURABLE DIGITAL SIGNAL PROCESSING (DSP) VECTOR ENGINE von RATHORE UNEEB YAQUB, WEBER SCOTT JEREMY, SHEIKH FARHANA, NAGI SUMEET SINGH

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