In situ surface and interface study of crystalline (3×1)-O on InAs von Qin, Xiaoye, Wang, Wei-E., Rodder, Mark S., Wallace, Robert M.

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A crystalline oxide passivation on In0.53Ga0.47As (100) von Qin, Xiaoye, Wang, Wei-E, Droopad, Ravi, Rodder, Mark S., Wallace, Robert M.

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A Multi-Bit Neuromorphic Weight Cell Using Ferroelectric FETs, suitable for SoC Integration von Obradovic, Borna, Rakshit, Titash, Hatcher, Ryan, Kittl, Jorge, Sengupta, Rwik, Hong, Joon Goo, Rodder, Mark S.

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Modeling Transient Negative Capacitance in Steep-Slope FeFETs von Obradovic, Borna, Rakshit, Titash, Hatcher, Ryan, Kittl, Jorge A., Rodder, Mark S.

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Lower limits of line resistance in nanocrystalline back end of line Cu interconnects von Hegde, Ganesh, Bowen, R. Chris, Rodder, Mark S.

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Band-to-Band Tunneling in Ge-Rich SiGe Devices von Obradovic, Borna, Bowen, Robert C., Rodder, Mark S.

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Modulation of the Schottky Barrier Height for CMOS advanced contacts von Menghini, Mariela A., Homm, Pia, Su, Chen-Yi, Kittl, Jorge A., Tomita, Ryuji, Hegde, Ganesh, Lee, Joon-Gon, Hyun, Sangjin, Bowen, Chris, Rodder, Mark.S., Afanas'ev, Valeri, Locquet, Jean-Pierre

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METHOD OF FORMING MULTIPLE-VT FETS FOR CMOS CIRCUIT APPLICATIONS von Wang, Wei-E, Rodder, Mark S

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Method of forming multiple-Vt FETS for CMOS circuit applications von Wang, Wei-E, Rodder, Mark S

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FIELD EFFECT TRANSISTOR WITH STACKED NANOWIRE-LIKE CHANNELS AND METHODS OF MANUFACTURING THE SAME von RODDER MARK S, OBRADOVIC BORNA

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HIGH-DENSITY NEUROMORPHIC COMPUTING ELEMENT von Rodder, Mark S, Obradovic, Borna J, Rakshit, Titash

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High-density neuromorphic computing element von Rodder, Mark S, Obradovic, Borna J, Rakshit, Titash

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3 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME von WANG WEI E, RODDER MARK S, GEROUSIS VASSILIOS

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METHOD OF FORMING MULTIPLE-VT FETS FOR CMOS CIRCUIT APPLICATIONS von Wang, Wei-E, Rodder, Mark S

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HIGH-DENSITY NEUROMORPHIC COMPUTING ELEMENT von Rodder, Mark S, Obradovic, Borna J, Rakshit, Titash

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GATE-ALL-AROUND NANOSHEET FIELD-EFFECT TRANSISTORS AND METHODS OF MANUFACTURING THE SAME von RODDER MARK S, HONG, JOON GOO

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3D METHOD OF FORMING A THERMAL SHIELD IN A MONOLITHIC 3-D INTEGRATED CIRCUIT von WANG WEI E, RODDER MARK S, GEROUSIS VASSILIOS

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Method of forming multiple-Vt FETs for CMOS circuit applications von Wang, Wei-E, Rodder, Mark S

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Method of forming a thermal shield in a monolithic 3-d integrated circuit von Wang, Wei-E, Rodder, Mark S, Gerousis, Vassilios

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SEMICONDUCTOR CELL BLOCKS HAVING NON-INTEGER MULTIPLE OF CELL HEIGHTS von Abaya, Tanya, Sengupta, Rwik, Hong, Joon Goo, Gerousis, Vassilios, Rodder, Mark S, Traynor, Kevin, Palle, Dharmendar

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