Vertical GAAFETs for the Ultimate CMOS Scaling von Yakimets, Dmitry, Eneman, Geert, Schuddinck, Pieter, Trong Huynh Bao, Bardon, Marie Garcia, Raghavan, Praveen, Veloso, Anabela, Collaert, Nadine, Mercha, Abdelkarim, Verkest, Diederik, Voon-Yew Thean, Aaron, De Meyer, Kristin

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Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI von Hills, Gage, Bardon, Marie Garcia, Doornbos, Gerben, Yakimets, Dmitry, Schuddinck, Pieter, Baert, Rogier, Doyoung Jang, Mattii, Luca, Sherazi, Syed Muhammed Yasser, Rodopoulos, Dimitrios, Ritzenthaler, Romain, Chi-Shuen Lee, Thean, Aaron Voon-Yew, Radu, Iuliana, Spessot, Alessio, Debacker, Peter, Catthoor, Francky, Raghavan, Praveen, Shulaker, Max M., Wong, H.-S Philip, Mitra, Subhasish

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Implications of BTI-Induced Time-Dependent Statistics on Yield Estimation of Digital Circuits von Weckx, Pieter, Kaczer, Ben, Toledano-Luque, Maria, Raghavan, Praveen, Franco, Jacopo, Roussel, Philippe J., Groeseneken, Guido, Catthoor, Francky

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Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes von Agarwal, Tarun kumar, Soree, Bart, Radu, Iuliana, Raghavan, Praveen, Iannaccone, Giuseppe, Fiori, Gianluca, Dehaene, Wim, Heyns, Marc

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Comparison of short-channel effects in monolayer MoS2 based junctionless and inversion-mode field-effect transistors von Agarwal, Tarun, Sorée, Bart, Radu, Iuliana, Raghavan, Praveen, Fiori, Gianluca, Iannaccone, Giuseppe, Thean, Aaron, Heyns, Marc, Dehaene, Wim

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Single- and multilayer graphene wires as alternative interconnects von Politou, Maria, Asselberghs, Inge, Soree, Bart, Lee, Chang Seung, Sayan, Safak, Lin, Dennis, Pashaei, Parham, Huyghebaert, Cedric, Raghavan, Praveen, Radu, Iuliana, Tokei, Zsolt, De Gendt, Stefan, Heyns, Marc

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Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node von Doyoung Jang, Yakimets, Dmitry, Eneman, Geert, Schuddinck, Pieter, Bardon, Marie Garcia, Raghavan, Praveen, Spessot, Alessio, Verkest, Diederik, Mocuta, Anda

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Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path von TANIGUCHI, Ittetsu, AOKI, Kohei, TOMIYAMA, Hiroyuki, RAGHAVAN, Praveen, CATTHOOR, Francky, FUKUI, Masahiro

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Low‐leakage sub‐threshold 9 T‐SRAM cell in 14‐nm FinFET technology von Zeinali, Behzad, Madsen, Jens Kargaard, Raghavan, Praveen, Moradi, Farshad

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Benchmarking of MoS2 FETs With Multigate Si-FET Options for 5 nm and Beyond von Agarwal, Tarun, Yakimets, Dmitry, Raghavan, Praveen, Radu, Iuliana, Thean, Aaron, Heyns, Marc, Dehaene, Wim

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Low-leakage sub-threshold 9T-SRAM cell in 14-nm FinFET technology von Zeinali, Behzad, Madsen, Jens Kargaard, Raghavan, Praveen, Moradi, Farshad

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Polarity control in WSe2 double-gate transistors von Resta, Giovanni V., Sutar, Surajit, Balaji, Yashwanth, Lin, Dennis, Raghavan, Praveen, Radu, Iuliana, Catthoor, Francky, Thean, Aaron, Gaillardon, Pierre-Emmanuel, de Micheli, Giovanni

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An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors von De Sutter, Bjorn, Allam, Osman, Raghavan, Praveen, Vandebriel, Roeland, Cappelle, Hans, Vander Aa, Tom, Mei, Bingfeng

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Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier von Agbo, Innocent, Taouil, Mottaqiallah, Kraak, Daniel, Hamdioui, Said, Kukner, Halil, Weckx, Pieter, Raghavan, Praveen, Catthoor, Francky

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Impact of Wire Geometry on Interconnect RC and Circuit Delay von Ciofi, Ivan, Contino, Antonino, Roussel, Philippe J., Baert, Rogier, Vega-Gonzalez, Victor H., Croes, Kristof, Badaroglu, Mustafa, Wilson, Christopher J., Raghavan, Praveen, Mercha, Abdelkarim, Verkest, Diederik, Groeseneken, Guido, Mocuta, Dan, Thean, Aaron

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Technology/Circuit/System Co-Optimization and Benchmarking for Multilayer Graphene Interconnects at Sub-10-nm Technology Node von Chenyun Pan, Raghavan, Praveen, Ceyhan, Ahmet, Catthoor, Francky, Tokei, Zsolt, Naeemi, Azad

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Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era von Sakhare, Sushil Sudam, Miyaguchi, Kenichi, Raghavan, Praveen, Mercha, Abdelkarim

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Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node von Chenyun Pan, Raghavan, Praveen, Yakimets, Dmitry, Debacker, Peter, Catthoor, Francky, Collaert, Nadine, Tokei, Zsolt, Verkest, Diederik, Thean, Aaron Voon-Yew, Naeemi, Azad

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Exchange-driven Magnetic Logic von Zografos, Odysseas, Manfrini, Mauricio, Vaysset, Adrien, Sorée, Bart, Ciubotaru, Florin, Adelmann, Christoph, Lauwereins, Rudy, Raghavan, Praveen, Radu, Iuliana P.

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A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs von Zeinali, Behzad, Madsen, Jens Kargaard, Raghavan, Praveen, Moradi, Farshad

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