Systematic Software-Based Self-Test for Pipelined Processors von Gizopoulos, D., Psarakis, M., Hatzimihail, M., Maniatakos, M., Paschalis, A., Raghunathan, A., Ravi, S.

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Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors von Apostolakis, A., Gizopoulos, D., Psarakis, M., Paschalis, A.

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Clinical Challenges in Caring for Patients With Diabetes and Cancer von Psarakis, Helen M.

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Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units von Xenoulis, G., Gizopoulos, D., Psarakis, M., Paschalis, A.

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Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip von Apostolakis, A., Psarakis, M., Gizopoulos, D., Paschalis, A.

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Built-in sequential fault self-testing of array multipliers von Psarakis, M., Gizopoulos, D., Paschalis, A.

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Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units von Xenoulis, G., Psarakis, M., Gizopoulos, D., Paschalis, A.

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MT-SBST: Self-test optimization in multithreaded multicore architectures von Foutris, N, Psarakis, M, Gizopoulos, D, Apostolakis, A, Vera, X, Gonzalez, A

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Sequential fault modeling and test pattern generation for CMOS iterative logic arrays von Psarakis, M., Gizopoulos, D., Paschalis, A., Zorian, Y.

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Chip Self-Organization and Fault Tolerance in Massively Defective Multicore Arrays von Collet, J H, Zajac, P, Psarakis, M, Gizopoulos, D

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Combining checkpointing and scrubbing in FPGA-based real-time systems von Sari, Aitzan, Psarakis, M., Gizopoulos, D.

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Deterministic software-based self-testing of embedded processor cores von Paschalis, A., Gizopoulos, D., Kranitis, N., Psarakis, M., Zorian, Y.

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Software-based self-test for pipelined processors: a case study von Hatzimihail, M., Xenoulis, G., Psarakis, M., Gizopoulos, D., Paschalis, A.

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Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools von Psarakis, M, Gizopoulos, D, Paschalis, A

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A methodology for detecting performance faults in microprocessors via performance monitoring hardware von Hatzimihail, M., Psarakis, M., Gizopoulos, D., Paschalis, A.

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An effective BIST architecture for fast multiplier cores von Paschalis, A., Gizopoulos, D., Kranitis, N., Psarakis, M., Zorian, Y.

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Test Program Generation for Communication Peripherals in Processor-Based SoC Devices von Apostolakis, A., Gizopoulos, D., Psarakis, M., Ravotto, D., Reorda, M.S.

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Robust and low-cost BIST architectures for sequential fault testing in datapath multipliers von Psarakis, M., Gizopoulos, D., Paschalis, A., Kranitis, N., Zorian, Y.

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Systematic software-based self-test for pipelined processors von Psarakis, Mihalis, Gizopoulos, Dimitris, Hatzimihail, Miltiadis, Paschalis, Antonis, Raghunathan, Anand, Ravi, Srivaths

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Evaluation of Xilinx Deep Learning Processing Unit under Neutron Irradiation von Agiakatsikas, D, Foutris, N, Sari, A, Vlagkoulis, V, Souvatzoglou, I, Psarakis, M, Luján, M, Kastriotou, M, Cazzaniga, C

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