Treffer 1 - 12 von 12 für Suche 'Pontikakis, Bill', Suchdauer: 0,98s Treffer weiter einschränken
  1. 1
    A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices

    A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices von Elbediwy, Mostafa, Pontikakis, Bill, David, Jean-Pierre, Savaria, Yvon

    Veröffentlicht in IEEE access

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  2. 2
    Enabling Rank-Based P4 Programmable Schedulers: Requirements, Implementation, and Evaluation on BMv2 Switches

    Enabling Rank-Based P4 Programmable Schedulers: Requirements, Implementation, and Evaluation on BMv2 Switches von Elbediwy, Mostafa, Pontikakis, Bill, David, Jean-Pierre, Savaria, Yvon


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  3. 3
    DR-PIFO: A Dynamic Ranking Packet Scheduler Using a Push-In-First-Out Queue

    DR-PIFO: A Dynamic Ranking Packet Scheduler Using a Push-In-First-Out Queue von Elbediwy, Mostafa, Pontikakis, Bill, Ghaffari, Alireza, David, Jean-Pierre, Savaria, Yvon


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  4. 4
    An all-digital skew-adaptive clock scheduling algorithm for heterogeneous multiprocessor systems on chips (MPSoCs)

    An all-digital skew-adaptive clock scheduling algorithm for heterogeneous multiprocessor systems on chips (MPSoCs) von Hasan, S.R., Pontikakis, B., Savaria, Y.


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  5. 5
    Precise free-running period synthesizer (FRPS) with process and temperature compensation

    Precise free-running period synthesizer (FRPS) with process and temperature compensation von Pontikakis, B., Boyer, F.-R., Savaria, Y., Hung Tien Bui


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  6. 6
    A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs

    A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs von Pontikakis, Bill, Bui, Hung Tien, Boyer, Francois-Raymond, Savaria, Yvon


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  7. 7
    A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs

    A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs von Pontikakis, B., Boyer, F.-R., Savaria, Y.


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  8. 8
    A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications

    A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications von Pontikakis, B., Nekili, M.

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  9. 9
    A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs

    A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs von Pontikakis, B., Hung Tien Bui, Boyer, F.-R., Savaria, Y.

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  10. 10
    Performance improvement of configurable processor architectures using a variable clock period

    Performance improvement of configurable processor architectures using a variable clock period von Pontikakis, B., Savaria, Y., Boyer, F.-R.

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  11. 11
    A new area-power efficient split-output TSPC CMOS latch for high-speed VLSI applications

    A new area-power efficient split-output TSPC CMOS latch for high-speed VLSI applications von Pontikakis, B., Nekili, M.

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  12. 12
    A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications

    A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications von Boyer, F.-R., Epassa, H.G., Pontikakis, B., Savaria, Y., Wei Ling

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