A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining von Barth, J.E., Anand, D., Burns, S., Dreibelbis, J.H., Fifield, J.A., Gorman, K., Nelms, M., Nelson, E., Paparelli, A., Pomichter, G., Pontius, D.E., Sliva, S.

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Embedded DRAM built in self test and methodology for test insertion von Jakobsen, P., Dreibelbis, J., Pomichter, G., Anand, D., Barth, J., Nelms, M., Leach, J., Belansek, G.

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A 500MHz multi-banked compilable DRAM macro with direct write and programmable pipelining von Barth, J., Anand, D., Dreibelbis, J., Fifield, J., Gorman, K., Nelms, M., Pomichter, G., Pontius, D.

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A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns von Jacunski, M, Anand, D, Busch, R, Fifield, J, Lanahan, M, Lane, P, Paparelli, A, Pomichter, G, Pontius, D, Roberge, M, Sliva, S

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Low Cost Test of High Bandwidth Embedded Memories von Gorman, K.W., Anand, D., Pomichter, G., Corbin, W.R.

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Advancements in at-speed array BIST: multiple improvements von Gorman, K., Roberge, M., Paparelli, A., Pomichter, G., Sliva, S., Corbin, W.

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A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST von Anand, D., Covino, J., Dreibelbis, J., Fifield, J., Gorman, K., Jacunski, M., Paparelli, J., Pomichter, G., Pontius, D., Roberge, M., Sliva, S.

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