A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods von Sedighiani, Shima, Singh, Kamlesh, Jordans, Roel, Harpe, Pieter, Gyvez, Jose Pineda de

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Twenty Years of Near/Sub-Threshold Design Trends and Enablement von Singh, Kamlesh, Pineda de Gyvez, Jose

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CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units von Xun Jiao, Rahimi, Abbas, Yu Jiang, Fatemi, Hamed, Pineda de Gyvez, Jose, Gupta, Rajesh K.

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Multi-Level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection von de Bruin, Barry, Singh, Kamlesh, Wang, Ying, Huisken, Jos, de Gyvez, Jose Pineda, Corporaal, Henk

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Logic Design Partitioning for Stacked Power Domains von Blutman, Kristof, Fatemi, Hamed, Kapoor, Ajay, Kahng, Andrew B., Jiajia Li, Pineda de Gyvez, Jose

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Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention von Ahmadi Balef, Hadi, Fatemi, Hamed, Goossens, Kees, Pineda De Gyvez, Jose

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Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique von Pavlov, A., Sachdev, M., Jose Pineda de Gyvez

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Multi-Angle Fusion for Low-Cost Near-Field Ultrasonic in-Air Gesture Recognition von Ibrahim, Emad A., Geilen, Marc, Li, Min, De Gyvez, Jose Pineda

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Editorial TVLSI Positioning-Continuing and Accelerating an Upward Trajectory von Alioto, Massimo

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Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation von Singh, Kamlesh, de Bruin, Barry, Jiao, Hailong, Huisken, Jos, Corporaal, Henk, de Gyvez, Jose Pineda

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Heuristic Methods for Fine-Grain Exploitation of FDSOI von Fatemi, Hamed, Kahng, Andrew B., Lee, Hyein, Pineda de Gyvez, Jose

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Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits von Meijer, M., de Gyvez, J. P.

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Enhancing sensitivity-based power reduction for an industry IC design context von Fatemi, Hamed, Kahng, Andrew B., Lee, Hyein, Li, Jiajia, Pineda de Gyvez, Jose

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Sub-Threshold Standard Cell Sizing Methodology and Library Comparison von Liu, Bo, De Gyvez, Jose, Ashouei, Maryam

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Prelayout interconnect yield prediction von Christie, P., Jose Pineda de Gyvez

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A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling von Blutman, Kristof, Kapoor, Ajay, Majumdar, Arjun, Martinez, Jacinto Garcia, Echeverri, Juan, Sevat, Leo, van der Wel, Arnoud P., Fatemi, Hamed, Makinwa, Kofi A. A., de Gyvez, Jose Pineda

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Idleness-Aware Dynamic Power Mode Selection on the i.MX 7ULP IoT Edge Processor von Di Mauro, Alfio, Fatemi, Hamed, de Gyvez, Jose Pineda, Benini, Luca

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An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage von Yu Pu, Pineda de Gyvez, J., Corporaal, H., Yajun Ha

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Fuzzy-Controlled Voltage Scaling Based on Supply Current Tracking von Pourshaghaghi, Hamid Reza, de Gyvez, Jose Pineda

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An Improved Methodology for Resilient Design Implementation von Kahng, Andrew B., Kang, Seokhyeong, Li, Jiajia, Pineda De Gyvez, Jose

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