Matching Performance of FinFET Devices With Fin Widths Down to 10 nm von Magnone, P., Mercha, A., Subramanian, V., Parvais, P., Collaert, N., Dehan, M., Decoutere, S., Groeseneken, G., Benson, J., Merelle, T., Lander, R.J.P., Crupi, F., Pace, C.

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Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession von Chiarella, T., Witters, L., Mercha, A., Kerner, C., Rakowski, M., Ortolland, C., Ragnarsson, L.-Å., Parvais, B., De Keersgieter, A., Kubicek, S., Redolfi, A., Vrancken, C., Brus, S., Lauwers, A., Absil, P., Biesemans, S., Hoffmann, T.

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Junctionless versus inversion-mode lateral semiconductor nanowire transistors von Veloso, A, Matagne, P, Simoen, E, Kaczer, B, Eneman, G, Mertens, H, Yakimets, D, Parvais, B, Mocuta, D

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Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs von ElKashlan, R. Y., Rodriguez, R., Yadav, S., Khaled, A., Peralagu, U., Alian, A., Waldron, N., Zhao, M., Wambacq, P., Parvais, B., Collaert, N.

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Analysis of the Gate Current's Influence on the RF Power Performance of InAlN/GaN HEMTs von Xiao, Dongping, Schreurs, Dominique M.M.-P, ElKashlan, Rana, Zhang, Yang, Cooman, Adam, Khaled, Ahmad, Smellie, Daanish, Alian, AliReza, Asad, Muhammad, Parvais, Bertrand, Wambacq, Piet, Peralagu, Uthayasankaran, Collaert, Nadine

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Analysis of the Gate Current's Influence on the RF Power Performance of InAlN/GaN HEMTs von Xiao, Dongping, Schreurs, Dominique M. M.-P., ElKashlan, Rana, Zhang, Yang, Cooman, Adam, Khaled, Ahmad, Smellie, Daanish, Alian, AliReza, Asad, Muhammad, Parvais, Bertrand, Wambacq, Piet, Peralagu, Uthayasankaran, Collaert, Nadine

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Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices von Ponton, D., Palestri, P., Esseni, D., Selmi, L., Tiebout, M., Parvais, B., Siprak, D., Knoblinger, G.

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A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability von Kaczer, B., Franco, J., Weckx, P., Roussel, Ph.J., Putcha, V., Bury, E., Simicic, M., Chasin, A., Linten, D., Parvais, B., Catthoor, F., Rzepa, G., Waltl, M., Grasser, T.

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High-Frequency Noise Performance of 60-nm Gate-Length FinFETs von Raskin, J.-P., Pailloncy, G., Lederer, D., Danneville, F., Dambrine, G., Decoutere, S., Mercha, A., Parvais, B.

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Gate dielectric material influence on DC behavior of MO(I)SHEMT devices operating up to 150 °C von Agopian, P.G.D., Carmo, G.J., Martino, J.A., Simoen, E., Peralagu, U., Parvais, B., Waldron, N., Collaert, N.

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(Plenary) The Revival of Compound Semiconductors and How They Will Change the World in a 5G/6G Era von Collaert, Nadine, Alian, AliReza, Banerjee, Aritra, Chauhan, Vikas, ElKashlan, Rana Y., Hsu, Brent, Ingels, Mark, Khaled, Ahmad, Kodandarama, Komal Vondkar, Kunert, Bernardette, Mols, Yves, Peralagu, Uthayasankaran, Putcha, Vamsi, Rodriguez, Raul, Sibaja-Hernandez, Arturo, Simoen, Eddy, Vais, Abhitosh, Walke, Amey, Witters, Liesbeth, Yadav, Sachin, Yu, Hao, Zhao, Ming, Wambacq, Piet, Parvais, Bertrand, Waldron, Niamh

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Determination and Validation of New Nonlinear FinFET Model Based on Lookup Tables von Crupi, G., Schreurs, D.M.M.-P., Dongping Xiao, Caddemi, A., Parvais, B., Mercha, A., Decoutere, S.

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(Invited) Defect Engineering for Monolithic Integration of III-V Semiconductors on Silicon Substrates von Claeys, Cor, Simoen, Eddy

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A low-power 57-to-66GHz transceiver in 40nm LP CMOS with −17dB EVM at 7Gb/s von Vidojkovic, V., Mangraviti, G., Khalaf, K., Szortyka, V., Vaesen, K., Van Thillo, W., Parvais, B., Libois, M., Thijs, S., Long, J. R., Soens, C., Wambacq, P.

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The Potential of FinFETs for Analog and RF Circuit Applications von Wambacq, P., Verbruggen, B., Scheir, K., Borremans, J., Dehan, M., Linten, D., De Heyn, V., Van der Plas, G., Mercha, A., Parvais, B., Gustin, C., Subramanian, V., Collaert, N., Jurczak, M., Decoutere, S.

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The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits von Kaczer, B., Franco, J., Weckx, P., Roussel, Ph.J., Simicic, M., Putcha, V., Bury, E., Cho, M., Degraeve, R., Linten, D., Groeseneken, G., Debacker, P., Parvais, B., Raghavan, P., Catthoor, F., Rzepa, G., Waltl, M., Goes, W., Grasser, T.

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Purely analytical extraction of an improved nonlinear FinFET model including non-quasi-static effects von Crupi, Giovanni, Schreurs, Dominique M.M.-P., Caddemi, Alina, Angelov, Iltcho, Homayouni, Majid, Raffo, Antonio, Vannini, Giorgio, Parvais, Bertrand

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Gate voltage and geometry dependence of the series resistance and of the carrier mobility in FinFET devices von Magnone, P., Subramanian, V., Parvais, B., Mercha, A., Pace, C., Dehan, M., Decoutere, S., Groeseneken, G., Crupi, F., Pierro, S.

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Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems von Flandre, D, Adriaensen, S, Akheyar, A, Crahay, A, Demeûs, L, Delatte, P, Dessard, V, Iniguez, B, Nève, A, Katschmarskyj, B, Loumaye, P, Laconte, J, Martinez, I, Picun, G, Rauly, E, Renaux, C, Spôte, D, Zitout, M, Dehan, M, Parvais, B, Simon, P, Vanhoenacker, D, Raskin, J.-P

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A four-path 60GHz phased-array receiver with injection-locked LO, hybrid beamforming and analog baseband section in 90nm CMOS von Raczkowski, K., Mangraviti, G., Szortyka, V., Spagnolo, A., Parvais, B., Vandebriel, R., Vidojkovic, V., Soens, C., D'Amico, S., Wambacq, P.

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