A reconfigurable high-speed and low-complexity residue number system-based multiply-accumulate channel filter for software radio receivers von Britto, Pari J, Mariammal, K, Vaithiyanathan, D

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Reconfigurable Architecture for Noise Cancellation in Acoustic Environment Using Single Multiply Accumulate Adaline Filter von Ezilarasan, M. R., Britto Pari, J., Leung, Man-Fai

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Decisive structures for multirate FIR filter incorporating retiming and pipelining schemes von K, Mariammal, M, Hajira Banu, J, Britto Pari, Dhandapani, Vaithiyanathan

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Performance analysis of multi-scaling voltage level shifter for low-power applications von D, Vaithiyanathan, Kurmi, Megha Singh, Mishra, Alok Kumar, J, Britto Pari

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ANOPTIMIZED ARCHITECTURE FOR ADAPTIVE DIGITAL FILTER von Britto, Pari J, Joy, Vasantha Rani S P

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Reconfigurable architecture of RNS based high speed FIR filter von Pari, J Britto, Rani, S P Joy Vasantha

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Performance Analysis of Pulse Triggered Flip-Flop von Dhandapani, Vaithiyanathan, Alok Kumar Mishra, Thakur, Richa, Chopra, Urvashi, Britto Pari J

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Predictable FPGA Execution for Attentional Affirmation in Multi-Speaker Condition von Rajalakshmi, Ms. S., Remya, Ms. V., Pari, Dr. J. Britto

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Performance Analysis of Implicit Pulsed and Low-Glitch Power-Efficient Double-Edge-Triggered Flip-Flops Using C-Elements von Vaithiyanathan, D., Gupta, Vikrant, Kumar, Santosh, Mishra, Alok Kumar, Britto Pari, J.

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