High-speed VLSI architectures for the AES algorithm von Xinmiao Zhang, Parhi, K.K.

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On the Optimum Constructions of Composite Field for the AES Algorithm von Xinmiao Zhang, Parhi, K.K.

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High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform von Chao Cheng, Parhi, K.K.

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Design of low-error fixed-width modified booth multiplier von Kyung-Ju Cho, Kwang-Chul Lee, Jin-Gyun Chung, Parhi, K.K.

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Hardware efficient fast parallel FIR filter structures based on iterated short convolution von Chao Cheng, Parhi, K.K.

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Overlapped message passing for quasi-cyclic low-density parity check codes von Yanni Chen, Parhi, K.K.

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Eliminating the fanout bottleneck in parallel long BCH encoders von Parhi, K.K.

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High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming von Chao Cheng, Parhi, K.K.

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Joint (3,k)-regular LDPC code and decoder/encoder design von Tong Zhang, Parhi, K.K.

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Hardware Efficient Fast DCT Based on Novel Cyclic Convolution Structures von Chao Cheng, Parhi, K.K.

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Design of multigigabit multiplexer-loop-based decision feedback equalizers von Parhi, K.K.

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A novel systolic array structure for DCT von Chao Cheng, Parhi, K.K.

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Fast factorization architecture in soft-decision Reed-Solomon decoding von Xinmiao Zhang, Parhi, K.K.

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High-speed architectures for parallel long BCH encoders von Xinmiao Zhang, Parhi, K.K.

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Small area parallel Chien search architectures for long BCH codes von Yanni Chen, Parhi, K.K.

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Systematic design of original and modified Mastrovito multipliers for general irreducible polynomials von Tong Zhang, Parhi, K.K.

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Low-Cost Fast VLSI Algorithm for Discrete Fourier Transform von Chao Cheng, Parhi, K.K.

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Low-Latency Low-Complexity Architectures for Viterbi Decoders von Renfei Liu, Parhi, K.K.

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Hardware Efficient Low-Latency Architecture for High Throughput Rate Viterbi Decoders von Chao Cheng, Parhi, K.K.

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An improved pipelined MSB-first add-compare select unit structure for Viterbi decoders von Parhi, K.K.

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