A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking von Loke, A.L.S., Barnes, R.K., Wee, T.T., Oshima, M.M., Moore, C.E., Kennedy, R.R., Barnes, J.O., Zimmer, R.A., Arave, K.L., Pang, H.H.M., Cynkar, T.E., Volz, A.M., Pfiester, J.R., Martin, R.J., Miller, R.H., Hood, D.A., Motley, G.W., Rojas, E.J., Walley, T.M., Gilsdorf, M.J.

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