A Built-Off Self-Repair Scheme for Channel-Based 3D Memories von Liu, Hsuan-Hung, Lin, Bing-Yang, Wu, Cheng-Wen, Chiang, Wan-Ting, Mincent, Lee, Lin, Hung-Chih, Peng, Ching-Nen, Wang, Min-Jer

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A Local Parallel Search Approach for Memory Failure Pattern Identification von Bing-Yang Lin, Cheng-Wen Wu, Lee, Mincent, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

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A memory yield improvement scheme combining built-in self-repair and error correction codes von Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang

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Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch von Sen-Kuei Hsu, Hao Chen, Chung-Han Huang, Der-Jiann Liu, Wei-Hsun Lin, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

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Bandwidth enhancement in 3DIC CoWoS™ test using direct probe technology von Hao Chen, Jian-Ting Chen, Shang-Ju Lee, Ken Chou, Cheng-Bin Chen, Sen-Kuei Hsu, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

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Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package von Kai-Li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

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Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement von Lin, Bing-Yang, Chiang, Wan-Ting, Wu, Cheng-Wen, Lee, Mincent, Lin, Hung-Chih, Peng, Ching-Nen, Wang, Min-Jer

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Electromagnetic shielding during wafer stage testing von Wang, Mill-Jer, Wang, Hsien-Tang, Lai, Chi-Chang, Peng, Ching-Nen

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Testing holders for chip unit and die package von Wang, Mill-Jer, Lin, Hung-Chih, Liu, Kuo-Chuan, Chen, Hao, Peng, Ching-Nen

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Test circuit and method von Wang, Mill-Jer, Lin, Hung-Chih, Chen, Hao, Wang, Chuan-Ching, Peng, Ching-Nen, Hsu, Sen-Kuei

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TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE von PENG, Ching-Nen, CHEN, Hao, WANG, Mill-Jer, LIU, Kuo-Chuan, LIN, Hung-Chih

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Testing holders for chip unit and die package von Wang, Mill-Jer, Lin, Hung-Chih, Liu, Kuo-Chuan, Chen, Hao, Peng, Ching-Nen

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Three dimensional integrated circuit electrostatic discharge protection and prevention test interface von Wang, Mill-Jer, Lin, Hung-Chih, Cheng, Hao, Peng, Ching-Nen

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TEST CIRCUIT AND METHOD von Lin, Hung-Chih, WANG, Mill-Jer, Chen, Hao, Wang, Chuan-Ching, Peng, Ching-Nen, Hsu, Sen-Kuei

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Test circuit and method von Wang, Mill-Jer, Lin, Hung-Chih, Chen, Hao, Wang, Chuan-Ching, Peng, Ching-Nen, Hsu, Sen-Kuei

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Devices for high-density probing techniques and method of implementing the same von Wang, Mill-Jer, Lin, Hung-Chih, Lin, Wei-Hsun, Liu, De-Jian, Peng, Ching-Nen, Hsu, Sen-Kuei

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ELECTROMAGNETIC SHIELDING DURING WAFER STAGE TESTING von Wang, Mill-Jer, Wang, Hsien-Tang, Lai, Chi-Chang, Peng, Ching-Nen

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TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE von PENG, Ching-Nen, CHEN, Hao, WANG, Mill-Jer, LIU, Kuo-Chuan, LIN, Hung-Chih

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THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION AND PREVENTION TEST INTERFACE von Wang, Mill-Jer, Lin, Hung-Chih, Cheng, Hao, Peng, Ching-Nen

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Testing holders for chip unit and die package von Wang, Mill-Jer, Lin, Hung-Chih, Liu, Kuo-Chuan, Chen, Hao, Peng, Ching-Nen

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