Power-Gated 9T SRAM Cell for Low-Energy Operation von Oh, Tae Woo, Jeong, Hanwool, Kang, Kyoman, Park, Juhyun, Yang, Younghwi, Jung, Seong-Ook

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Current Measurement Transducer Based on Current-to-Voltage-to-Frequency Converting Ring Oscillator with Cascade Bias Circuit von Park, Jongha, Park, Jung-Hyun, Jung, Seong-Ook

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Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology von Younghwi Yang, Juhyun Park, Seung Chul Song, Wang, Joseph, Yeap, Geoffrey, Seong-Ook Jung

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Proton conductor von KWON KYUNG-JUNG,YANO MASAYA,SUN HEE-YOUNG,PARK JUNG-OOK

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All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash von An, Jun Ho, Chun, Jin Young, Park, Hyun Kook, Jung, Seong-Ook

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Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation von Oh, Tae Woo, Jeong, Hanwool, Park, Juhyun, Jung, Seong-Ook

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SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis von Choi, Tae Hoon, Jeong, Hanwool, Yang, Younghwi, Park, Juhyun, Jung, Seong-Ook

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Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation von Oh, Ji Sang, Park, Juhyun, Cho, Keonhee, Oh, Tae Woo, Jung, Seong-Ook

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An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache von Kim, Tae Hyun, Jeong, Hanwool, Park, Juhyun, Kim, Hoonki, Song, Taejoong, Jung, Seong-Ook

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Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution von Kim, Kiryong, Jeong, Hanwool, Park, Juhyun, Jung, Seong-Ook

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Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM von Junyoung Ko, Younghwi Yang, Jisu Kim, Younghoon Oh, Park, H. K., Seong-ook Jung

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EPOXY RESIN COMPOSITION AND HEAT DISSIPATION CIRCUIT BOARD USING THE SAME von YOON JONG HEUM, GIANG THANH KIEU, CHO IN HEE, PARK JAE MAN, KIM JIN HWAN, LEE JONG SIK, PARK JUNG-OOK, GIL GUN YOUNG, YUN SUN JIN, LEE HYUK SOO, KIM MYEONG JEONG

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Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation von Kang, Kyoman, Jeong, Hanwool, Yang, Younghwi, Park, Juhyun, Kim, Kiryong, Jung, Seong-Ook

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All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme von Jung, Dong-Hoon, Ryu, Kyungho, Park, Jung-Hyun, Jung, Seong-Ook

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Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM von Junyoung Ko, Jisu Kim, Youngdon Choi, Park, H. K., Seong-Ook Jung

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All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM von Jung, Dong-Hoon, An, Young-Jae, Ryu, Kyungho, Park, Jung-Hyun, Jung, Seong-Ook

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The Unique Relationship between Neuro-Critical Care and Critical Illness-Related Corticosteroid Insufficiency : Implications for Neurosurgeons in Neuro-Critical Care von Choo, Yoon Hee, Kim, Moinay, Kim, Jae Hyun, Jeon, Hanwool, Jung, Hee-Won, Ha, Eun Jin, Oh, Jiwoong, Shim, Youngbo, Kim, Seung Bin, Jung, Han-Gil, Park, So Hee, Kim, Jung Ook, Kim, Junhyung, Kim, Hyeseon, Lee, Seungjoo

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Design of a 22-nm FinFET-Based SRAM With Read Buffer for Near-Threshold Voltage Operation von Juhyun Park, Younghwi Yang, Hanwool Jeong, Seung Chul Song, Wang, Joseph, Yeap, Geoffrey, Seong-Ook Jung

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GRO‐TDC with gate‐switch‐based delay cell halving resolution limit von Park, Jung‐Hyun, Jung, Dong‐Hoon, Jung, Seong‐Ook

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SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit von Younghwi Yang, Juhyun Park, Seung Chul Song, Wang, Joseph, Yeap, Geoffrey, Seong-Ook Jung

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