Hardware Implementation of Code Converters Designed to Reduce the Length of Binary Encoded Words von Bibilo, P. N.

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Minimizing Binary Decision Diagrams for Systems of Incompletely Defined Boolean Functions Using Algebraic Cofactor Expansions von Bibilo, P. N.

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Application of decision diagrams of incompletely specified of k-valued logic functions in the synthesis of logical circuits von Bibilo, P. N.

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Circuit Implementation of Modular Adders in Custom CMOS VLSI and FPGA von Bibilo, P. N., Kirienko, N. A.

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Technology independent optimization when implementing sparse systems of disjunctive normal forms of Boolean functions in ASIC von Bibilo, P. N., Kardash, S. N.

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Experimental Study of Algorithms for Minimization of Binary Decision Diagrams Using Algebraic Representations of Cofactors von Bibilo, P. N., Romanov, V. I.

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Decomposing a System of Boolean Functions into Subsystems of Connected Functions von Bibilo, P. N.

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Experimental comparison of the effectiveness of programs for minimizing systems of Boolean functions in the class of disjunctive normal forms von Bibilo, P. N., Loginova, I. P.

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Estimation of the energy consumption of digital devices represented by a composition of a control FSM and an arithmetic and logic unit von Bibilo, P. N.

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Minimization of binary decision diagrams for systems of completely defined Boolean functions using Shannon expansions and algebraic representations of cofactors von Bibilo, P. N., Romanov, V. I.

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The search for subsystems of related functions from multilevel representation of systems of Boolean functions1 von Bibilo, P. N., Pazniak, A. M.

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Logical minimization for combinatorial structure in FPGA von Bibilo, P. N., Lankevich, Yu. Yu, Romanov, V. I.

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Decomposition of a system of incompletely specified Boolean functions defined with a binary decision diagram von Bibilo, P. N.

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Verification and Scheme Implementation of Parallel Automata von Avdeev, N. A., Bibilo, P. N., Romanov, V. I.

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Minimization of binary decision diagrams for systems of incompletely defined Boolean functions von Bibilo, P. N.

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Experimental comparison of decomposition methods for systems of Boolean function von Avdeev, N. A., Bibilo, P. N.

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A System for Logical Design of Custom CMOS VLSI Functional Blocks with Reduced Power Consumption von Bibilo, P. N., Avdeev, N. A., Kardash, S. N., Kirienko, N. A., Lankevich, Yu. Yu, Loginova, I. P., Romanov, V. I., Cheremisinov, D. I., Cheremisinova, L. D.

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Decomposition of systems of Boolean functions determined by binary decision diagrams von Bibilo, P. N., Leonczyk, P. V.

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CIRCUIT IMPLEMENTATION OF VHDL-DESCRIPTIONS OF SYSTEMS OF PARTIAL BOOLEAN FUNCTIONS von P. N. Bibilo

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Logical optimization of Boolean nets using Shannon expansion von P. N. Bibilo, Yu. Y. Lankevich

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