Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession von Chiarella, T., Witters, L., Mercha, A., Kerner, C., Rakowski, M., Ortolland, C., Ragnarsson, L.-Å., Parvais, B., De Keersgieter, A., Kubicek, S., Redolfi, A., Vrancken, C., Brus, S., Lauwers, A., Absil, P., Biesemans, S., Hoffmann, T.

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Stress Memorization Technique-Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process von Ortolland, C., Okuno, Y., Verheyen, P., Kerner, C., Stapelmann, C., Aoulaiche, M., Horiguchi, N., Hoffmann, T.

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New carbon-based thermal stability improvement technique for NiPtSi used in CMOS technology von Ortolland, C., Togo, M., Rosseel, E., Mertens, S., Kittl, J., Absil, P.P., Lauwers, A., Hoffmann, T.

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Laser annealed junctions: Pocket profile analysis using an atomistic kinetic Monte Carlo approach von Noda, T, Ortolland, C, Vandervorst, W, Vrancken, C, Rosseel, E, Clarysse, T, Absil, P P, Biesemans, S, Hoffmann, T

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On the 'permanent' component of NBTI von Grasser, T, Aichinger, Th, Reisinger, H, Franco, J, Wagner, P.-J, Nelhiebel, M, Ortolland, C, Kaczer, B

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High-mobility Si1−xGex-channel PFETs: Layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths von Eneman, G, Yamaguchi, S, Ortolland, C, Takeoka, S, Witters, L, Chiarella, T, Favia, P, Hikavyy, A, Mitard, J, Kobayashi, M, Krom, R, Bender, H, Tseng, J, Wang, W, Vandervorst, W, Loo, R, Absil, P P, Biesemans, S, Hoffmann, T

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Ion-implantation-based low-cost Hk/MG process for CMOS low-power application von Ortolland, C, Sahhaf, S, Srividya, V, Degraeve, R, Saino, K, Kim, C S, Gilbert, M, Kauerauf, T, Cho, M J, Dehan, M, Schram, T, Togo, M, Horiguchi, N, Groeseneken, G, Biesemans, S, Absil, P P, Vandervorst, W, Gealy, D, Hoffmann, T

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Method for Managing the Stress Due to the Strained Nitride Capping Layer in MOS Transistors von Orain, Stphane, Fiori, Vincent, Villanueva, Davy, Dray, Alexandre, Ortolland, Claude

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Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? von Chiarella, T., Witters, L., Mercha, A., Kerner, C., Dittrich, R., Rakowski, M., Ortolland, C., Ragnarsson, L.-A., Parvais, B., De Keersgieter, A., Kubicek, S., Redolfi, A., Rooyackers, R., Vrancken, C., Brus, S., Lauwers, A., Absil, P., Biesemans, S., Hoffmann, T.

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Stress Memorization Technique (SMT) Optimization for 45nm CMOS von Ortolland, C., Morin, P., Chaton, C., Mastromatteo, E., Populaire, C., Orain, S., Leverd, F., Stolk, P., Boeuf, F., Arnaud, F.

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Nonuniform Mobility-Enhancement Techniques and Their Impact on Device Performance von Payet, Fabrice, Boeuf, Frederic, Ortolland, Claude, Skotnicki, Thomas

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Coulomb-blockade in nanometric Si-film silicon-on-nothing (SON) MOSFETs von Monfray, S., Souifi, A., Boeuf, F., Ortolland, C., Poncet, A., Militaru, L., Chanemougame, D., Skotnicki, T.

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65 nm LP/GP mix low cost platform for multi-media wireless and consumer applications von Tavel, B., Duriez, B., Gwoziecki, R., Basso, M.T., Julien, C., Ortolland, C., Laplanche, Y., Fox, R., Sabouret, E., Detcheverry, C., Boeuf, F., Morin, P., Barge, D., Bidaud, M., Biénacel, J., Garnier, P., Cooper, K., Chapon, J.D., Trouiller, Y., Belledent, J., Broekaart, M., Gouraud, P., Denais, M., Huard, V., Rochereau, K., Difrenza, R., Planes, N., Marin, M., Boret, S., Gloria, D., Vanbergue, S., Abramowitz, P., Vishnubhotla, L., Reber, D., Stolk, P., Woo, M., Arnaud, F.

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Layout Scaling of \hbox\hbox \hbox pFETs von Eneman, G., Yamaguchi, S., Ortolland, C., Takeoka, S., Kobayashi, M., Witters, L., Hikavyy, A., Mitard, J., Loo, R., Hoffmann, T.

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Calibrated Mobility Corrections for Drift Diffusion Simulation of Strained MOSFET Devices von Villanueva, D., Dray, A., Orain, V.S., Fiori, C., Ortolland, E., Fuchs, E., Salvetti, F., Juge, A.

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Stress Memorization TechniqueaFundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process von Ortolland, C, Okuno, Y, Verheyen, P, Kerner, C, Stapelmann, C, Aoulaiche, M, Horiguchi, N, Hoffmann, T

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A New Quasi Ballistic Model for Strained MOSFET von Fuchs, E., Orain, S., Ortolland, C., Dollfus, P., Le Carval, G., Villanueva, D., Dray, A., Jaouen, H., Skotnicki, T.

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65nm LP/GP mix low cost platform for multi-media wireless and consumer applications von Tavel, B., Duriez, B., Gwoziecki, R., Basso, M.T., Julien, C., Ortolland, C., Laplanche, Y., Fox, R., Saboure, E., Detcheverry, C., Boeuf, F., Morin, P., Barge, D., Bidaud, M., Bienacel, J., Garnier, P., Cooper, K., Chapon, J.D., Trouille, Y., Belledent, J., Broekaart, M., Gouraud, P., Denais, M., Huard, V., Rochereau, K., Difrenza, R., Planes, N., Marin, M., Boret, S., Gloria, D., Vanbergue, S., Abramowitz, P., Vishnubhotla, L., Reber, D., Stolk, P., Woo, M., Arnaud, F.

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Analysis of pocket profile deactivation and its impact on Vth variation for Laser annealed device using an atomistic kinetic Monte Carlo approach von Noda, T, Vandervorst, W, Vrancken, C, Ortolland, C, Rosseel, E, Eyben, P, Absil, P P, Biesemans, S, Hoffmann, T Y

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Overview of anneal technology for advanced logic CMOS von Ortolland, C.

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