Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems von Chen Kong Teh, Hamada, M., Fujita, T., Hara, H., Ikumi, N., Oowaki, Y.

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A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling von Fujiyoshi, T., Shiratake, S., Nomura, S., Nishikawa, T., Kitasho, Y., Arakida, H., Okuda, Y., Tsuboi, Y., Hamada, M., Hara, H., Fujita, T., Hatori, F., Shimazawa, T., Yahagi, K., Takeda, H., Murakata, M., Minami, F., Kawabe, N., Kitahara, T., Seta, K., Takahashi, M., Oowaki, Y., Furuyama, T.

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A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive von Takashima, D., Shuto, S., Kunishima, I., Takenaka, H., Oowaki, Y., Tanaka, S.

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Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs von Noguchi, M., Numata, T., Mitani, Y., Shino, T., Kawanaka, S., Oowaki, Y., Toriumi, A.

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A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's von Watanabe, S., Tsuchida, K., Takashima, D., Oowaki, Y., Nitayama, A., Hieda, K., Takato, H., Sunouchi, K., Horiguchi, F., Ohuchi, K., Masuoka, F., Hara, H.

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A novel power-off mode for a battery-backup DRAM von Takashima, D., Oowaki, Y.

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Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's von Takashima, D., Oowaki, Y., Watanabe, S., Ohuchi, K.

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A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI von Hamada, M., Hara, H., Fujita, T., Chen Kong Teh, Shimazawa, T., Kawabe, N., Kitahara, T., Kikuchi, Y., Nishikawa, T., Takahashi, M., Oowaki, Y.

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A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing von Miyashita, D., Yamaki, R., Hashiyoshi, K., Kobayashi, H., Kousai, S., Oowaki, Y., Unekawa, Y.

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Standby/active mode logic for sub-1-V operating ULSI memory von Takashima, D., Watanabe, S., Nakano, H., Oowaki, Y., Ohuchi, K., Tango, H.

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Session 2 overview - non-volatile memory von Sofer, Y., Oowaki, Y.

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An experimental DRAM with a NAND-structured cell von Hasegawa, T., Takashima, D., Ogiwara, R., Ohta, M., Shiratake, S.-I., Hamamoto, T., Yamada, T., Aoki, M., Ishibashi, S., Oowaki, Y., Watanabe, S., Masuoka, F.

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A 33-ns 64-Mb DRAM von Oowaki, Y., Tsuchida, K., Watanabe, Y., Takashima, D., Ohta, M., Nakano, H., Watanabe, S., Nitayama, A., Horiguchi, F., Ohuchi, K., Masuoka, F.

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A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm von Kikuchi, Yu, Takahashi, M., Maeda, T., Hara, H., Arakida, H., Yamamoto, H., Hagiwara, Y., Fujita, T., Watanabe, M., Shimazawa, T., Ohara, Y., Miyamori, T., Hamada, M., Oowaki, Y.

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A 76-mm(2) 8-Mb chain ferroelectric memory von Takashima, D, Takeuchi, Y, Miyakawa, T, Itoh, Y, Ogiwara, R, Kamoshida, M, Hoya, K, Doumae, S M, Ozaki, T, Kanaya, H, Yamakawa, K, Kunishima, I, Oowaki, Y

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Word-line architecture for highly reliable 64-Mb DRAM von Takashima, D., Oowaki, Y., Ogiwara, R., Watanabe, Y., Tsuchida, K., Ohta, M., Nakano, H., Watanabe, S., Ohuchi, K.

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New nibbled-page architecture for high-density DRAMs von Numata, K., Oowaki, Y., Itoh, Y., Hara, T., Tsuchida, K., Ohta, M., Watanabe, S., Ohuchi, K.

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Open/folded bit-line arrangement for ultra-high-density DRAM's von Takashima, D., Watanabe, S., Nakano, H., Oowaki, Y., Ohuchi, K.

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The stabilized reference-line (SRL) technique for scaled DRAMs von Tsuchida, K., Oowaki, Y., Ohta, M., Takashima, D., Watanabe, S., Ohuchi, K., Masuoka, F.

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VIB-1 new hot-carrier-induced degradation phenomena in half-micrometer MOS transistors von Nitayama, A., Takenouchi, N., Hamamoto, T., Oowaki, Y.

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