Complexity of Spectrum Activity and Benefits of Reinforcement Learning for Dynamic Channel Selection von Macaluso, Irene, Finn, Danny, Ozgul, Baris, DaSilva, Luiz A.

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Software-programmable digital pre-distortion on new generation FPGAs von Özgül, Barış, Langer, Jan, Noguera, Juanjo, Vissers, Kees

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AMD XDNA™ NPU in Ryzen™ AI Processors von Rico, Alejandro, Pareek, Satyaprakash, Cabezas, Javier, Clarke, David, Ozgul, Baris, Barat, Francisco, Fu, Yao, Munz, Stephan, Stuart, Dylan, Schlangen, Patrick, Duarte, Pedro, Date, Sneha, Paul, Indrani, Weng, Jian, Santan, Sonal, Kathail, Vinod, Sirasao, Ashish, Noguera, Juanjo

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Spectrum and Energy Efficient Block Edge Mask-Compliant Waveforms for Dynamic Environments von Macaluso, Irene, Ozgul, Baris, Forde, Timothy K., Sutton, Paul, Doyle, Linda

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Orthogonal space-time block coding for continuous phase modulation with frequency-domain equalization von Ozgul, B., Koca, M., Delic, H.

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Double Turbo Equalization of Continuous Phase Modulation with Frequency Domain Processing von Ozgul, B., Koca, M., Delic, H.

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Doubly Iterative Equalization of Continuous-Phase Modulation von Ozgul, B., Koca, M., Delic, H.

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Wireless access with blind collision-multiplicity detection and retransmission diversity for quasi-static channels von Ozgul, B., Delic, H.

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Pre-Equalization for Continuous Phase Modulation von Ozgul, Baris, Koca, M., Delic, H., Stuber, G. L.

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VECTORIZED PEAK DETECTION FOR SIGNAL PROCESSING von OZGUL, Baris, BARMAN, Kaushik, DIGHE, Parag, DATE, Sneha Bhalchandra

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Device with data processing engine array that enables partial reconfiguration von Langer, Jan, Date, Sneha Bhalchandra, Ozgul, Baris, Bilski, Goran H. k, Noguera Serra, Juan J

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DATA PROCESSING ENGINE TILE ARCHITECTURE FOR AN INTEGRATED CIRCUIT von NOGUERA SERRA, Juan, J, OZGUL, Baris, BILSKI, Goran, H.K, DATE, Sneha, Bhalchandra, LANGER, Jan, CLARKE, David

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Space-frequency coded HIPERLAN/2 von Esli, C., Ozgul, B., Delic, H.

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DEVICE WITH DATA PROCESSING ENGINE ARRAY THAT ENABLES PARTIAL RECONFIGURATION von NOGUERA SERRA, Juan J, OZGUL, Baris, BILSKI, Goran Hk, DATE, Sneha Bhalchandra, LANGER, Jan

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Communicating between data processing engines using shared memory von Bilski, Goran Hk, Langer, Jan, Ozgul, Baris, Noguera Serra, Juan J

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Multiple overlays for use with a data processing array von Stuart, Dylan, Münz, Stephan, Ozgul, Baris, Duarte, Pedro Miguel Parola, Clarke, David, Noguera Serra, Juan J, McColgan, Peter

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Dual mode interconnect von Bilski, Goran Hk, Langer, Jan, Ozgul, Baris, Clarke, David, Noguera Serra, Juan J, McColgan, Peter

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DEVICE WITH DATA PROCESSING ENGINE ARRAY THAT ENABLES PARTIAL RECONFIGURATION von NOGUERA SERRA, Juan J, OZGUL, Baris, DATE, Sneha Bhalchandra, BILSKI, Goran H.k, LANGER, Jan

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MULTIPLE OVERLAYS FOR USE WITH A DATA PROCESSING ARRAY von NOGUERA SERRA, Juan, J, OZGUL, Baris, DUARTE, Pedro, Miguel Parola, MÜNZ, Stephan, MCCOLGAN, Peter, STUART, Dylan, CLARKE, David

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VECTORIZED PEAK DETECTION FOR SIGNAL PROCESSING von OZGUL, Baris, BARMAN, Kaushik, DIGHE, Parag, DATE, Sneha Bhalchandra

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