High-k/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length von KHATER, Marwan H, ZHEN ZHANG, YU ZHU, YING ZHANG, CHOI, Changhwan, FRANK, Martin M, LEE, Kam-Leung, NARAYANAN, Vijay, PARK, Dae-Gyu, QIQING OUYANG, HAENSCH, Wilfried, JIN CAI, LAVOIE, Christian, D'EMIC, Christopher, QINGYUN YANG, BIN YANG, GUILLORN, Michael, KLAUS, David, OTT, John A

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High- \kappa/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length von Khater, M.H., Zhen Zhang, Jin Cai, Lavoie, C., D'Emic, C., Qingyun Yang, Bin Yang, Guillorn, M., Klaus, D., Ott, J.A., Yu Zhu, Ying Zhang, Changhwan Choi, Frank, M.M., Kam-Leung Lee, Narayanan, V., Dae-Gyu Park, Qiqing Ouyang, Haensch, W.

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Modeling of direct tunneling current through gate dielectric stacks von Mudanai, S., Yang-Yu Fan, Qiqing Ouyang, Tasch, A.F., Banerjee, S.K.

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Simulation Study of Reduced Self-Heating in Novel Thin-SOI Vertical Bipolar Transistors von Qiqing Ouyang, Kai Xiu

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High speed lateral trench detectors with a junction substrate von Qiqing Ouyang, Schaub, J.D.

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A novel Si/SiGe heterojunction pMOSFET with reduced short-channel effects and enhanced drive current von Qiqing Ouyang, Xiangdong Chen, Mudanai, S.P., Xin Wang, Kencke, D.L., Tasch, A.F., Register, L.F., Banerjee, S.K.

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Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates von Qiqing Ouyang, Min Yang, Holt, J., Panda, S., Huajie Chen, Utomo, H., Fischetti, M., Rovedo, N., Jinghong Li, Klymko, N., Wildman, H., Kanarsky, T., Costrini, G., Fried, D.M., Bryant, A., Ott, J.A., Meikei Ieong, Chun-Yung Sung

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Simulation Analysis of Series Resistance for SOI MOSFET in Nanometer Regime von Xinlin Wang, Oldiges, P., Bryant, A., Jin Cai, Qiqing Ouyang, Rim, K.

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Detection of defect in edge device manufacturing by artificial intelligence von Ouyang, Qiqing Christine, Khapov, Igor

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DETECTION OF DEFECT IN EDGE DEVICE MANUFACTURING BY ARTIFICIAL INTELLIGENCE von Ouyang, Qiqing Christine, Khapov, Igor

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Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping von Xiangdong Chen, Ouyang, Q.C., Geng Wang, Banerjee, S.K.

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High-[Formula Omitted]/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length von Khater, Marwan H, Zhang, Zhen, Cai, Jin, Lavoie, Christian, D'Emic, Christopher, Yang, Qingyun, Yang, Bin, Guillorn, Michael, Klaus, David, Ott, John A, Zhu, Yu, Zhang, Ying, Choi, Changhwan, Frank, Martin M, Lee, Kam-Leung, Narayanan, Vijay, Park, Dae-Gyu, Ouyang, Qiqing, Haensch, Wilfried

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Strain for CMOS performance improvement von Chan, V., Ken Rim, Meikei Ieong, Sam Yang, Rajeev Malik, Young Way Teh, Min Yang, Qiqing

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Data classification for data lake catalog von Ramos, Jo A, Moura, Marcio T, Rangarao, Deepak, Ouyang, Qiqing C

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Data classification for data lake catalog von Ramos, Jo A, Moura, Marcio T, Rangarao, Deepak, Ouyang, Qiqing C

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Hole and electron mobility enhancement in strained SiGe vertical MOSFETs von Xiangdong Chen, Kou-Chen Liu, Ouyang, Q.C., Jayanarayanan, S.K., Banerjee, S.K.

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Modeling environment noise for training neural networks von Kwatra, Shikhar, Reiss, Gary William, Ouyang, Qiqing Christine, Baughman, Aaron K

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SiGe FinFET with improved junction doping control von Kerber, Pranita, Reznicek, Alexander, Ouyang, Qiqing C

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Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step von Schepis, Dominic J, Kerber, Pranita, Reznicek, Alexander, Ouyang, Qiqing C

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Reduced resistance short-channel InGaAs planar MOSFET von Kerber, Pranita, Reznicek, Alexander, Ouyang, Qiqing C

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