An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing von Miyashita, Daisuke, Yamaki, Ryo, Hashiyoshi, Kazunori, Kobayashi, Hiroyuki, Kousai, Shouhei, Oowaki, Yukihito, Unekawa, Yasuo

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A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM von Kikuchi, Yu, Takahashi, Makoto, Maeda, Tomohisa, Fukuda, Masatoshi, Koshio, Yasuhiro, Hara, Hiroyuki, Arakida, Hideho, Yamamoto, Hideaki, Hagiwara, Yousuke, Fujita, Tetsuya, Watanabe, Manabu, Ezawa, Hirokazu, Shimazawa, Takayoshi, Ohara, Yasuo, Miyamori, Takashi, Hamada, Mototsugu, Takahashi, Masafumi, Oowaki, Yukihito

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Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems von Chen Kong Teh, Hamada, M., Fujita, T., Hara, H., Ikumi, N., Oowaki, Y.

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A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing von Miyashita, D., Yamaki, R., Hashiyoshi, K., Kobayashi, H., Kousai, S., Oowaki, Y., Unekawa, Y.

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19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension von Watanabe, Konosuke, Yoshii, Kenichiro, Kondo, Nobuhiro, Maeda, Kenichi, Fujisawa, Toshio, Wadatsumi, Junji, Miyashita, Daisuke, Kousai, Shouhei, Unekawa, Yasuo, Fujii, Shinsuke, Aoyama, Takuma, Tamura, Takayuki, Kunimatsu, Atsushi, Oowaki, Yukihito

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A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling von Fujiyoshi, T., Shiratake, S., Nomura, S., Nishikawa, T., Kitasho, Y., Arakida, H., Okuda, Y., Tsuboi, Y., Hamada, M., Hara, H., Fujita, T., Hatori, F., Shimazawa, T., Yahagi, K., Takeda, H., Murakata, M., Minami, F., Kawabe, N., Kitahara, T., Seta, K., Takahashi, M., Oowaki, Y., Furuyama, T.

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Electro-reflectance spectra of one-dimensional excitons in polydiacetylene crystals von Tokura, Yoshinori, Oowaki, Yukihito, Koda, Takao, Baughman, Ray H.

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A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm von Kikuchi, Yu, Takahashi, M., Maeda, T., Hara, H., Arakida, H., Yamamoto, H., Hagiwara, Y., Fujita, T., Watanabe, M., Shimazawa, T., Ohara, Y., Miyamori, T., Hamada, M., Oowaki, Y.

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A 76-mm(2) 8-Mb chain ferroelectric memory von Takashima, D, Takeuchi, Y, Miyakawa, T, Itoh, Y, Ogiwara, R, Kamoshida, M, Hoya, K, Doumae, S M, Ozaki, T, Kanaya, H, Yamakawa, K, Kunishima, I, Oowaki, Y

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Hot electron injection characteristics in asymmetrically structured submicron MOSFETs von OKABE, N, TAKATO, H, OOWAKI, Y, HAMAMOTO, T, NITAYAMA, A

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A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive von Takashima, D., Shuto, S., Kunishima, I., Takenaka, H., Oowaki, Y., Tanaka, S.

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Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs von Noguchi, M., Numata, T., Mitani, Y., Shino, T., Kawanaka, S., Oowaki, Y., Toriumi, A.

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An automated runtime power-gating scheme von Hamada, M., Kitahara, T., Kawabe, N., Sato, H., Nishikawa, T., Shimazawa, T., Yamashita, T., Hara, H., Oowaki, Y.

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Ferroelectric memory von OOWAKI, YUKIHITO

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A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's von Watanabe, S., Tsuchida, K., Takashima, D., Oowaki, Y., Nitayama, A., Hieda, K., Takato, H., Sunouchi, K., Horiguchi, F., Ohuchi, K., Masuoka, F., Hara, H.

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A novel power-off mode for a battery-backup DRAM von Takashima, D., Oowaki, Y.

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Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's von Takashima, D., Oowaki, Y., Watanabe, S., Ohuchi, K.

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A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI von Hamada, M., Hara, H., Fujita, T., Chen Kong Teh, Shimazawa, T., Kawabe, N., Kitahara, T., Kikuchi, Y., Nishikawa, T., Takahashi, M., Oowaki, Y.

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Random access memory with divided memory banks and data read/write architecture therefor von OOWAKI YUKIHITO

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Random access memory with divided memory banks and data read/write architecture therefor von Oowaki, Yukihito

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