Peptidase inhibitors in tick physiology von PARIZI, L. F., ALI, A., TIRLONI, L., OLDIGES, D. P., SABADIN, G. A., COUTINHO, M. L., SEIXAS, A., LOGULLO, C., TERMIGNONI, C., DA SILVA VAZ, I.

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Low-Energy Proton-Induced Single-Event-Upsets in 65 nm Node, Silicon-on-Insulator, Latches and Memory Cells von Rodbell, K.P., Heidel, D.F., Tang, H.H.K., Gordon, M.S., Oldiges, P., Murray, C.E.

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Meeting the Challenge of Multiple Threshold Voltages in Highly Scaled Undoped FinFETs von Muralidhar, R., Jin Cai, Frank, D. J., Oldiges, P., Lu, D., Lauer, I.

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The Propagation of Extended SET Tails in RF Amplifiers Using 45-nm CMOS on PDSOI von Teng, Jeffrey W., Ringel, Brett L., Brumbach, Zachary R., Heimerl, Justin P., Mensah, Yaw A., Tzintzarov, George N., Ildefonso, Adrian, Khachatrian, Ani, McMorrow, Dale, Oldiges, Phil, Cressler, John D.

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SALUS—a non-inferiority trial to compare self-tonometry in glaucoma patients with regular inpatient intraocular pressure controls: study design and set-up von Oldiges, Kristina, Steinmann, Maren, Duevel, Juliane Andrea, Gruhn, Sebastian, Diener, Raphael, Leclaire, Martin Dominik, Al-Nawaiseh, Sami, Eter, Nicole

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Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells von Heidel, D.F., Rodbell, K.P., Oldiges, P., Gordon, M.S., Tang, H.H.K., Cannon, E.H., Plettner, C.

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Latch Design Techniques for Mitigating Single Event Upsets in 65 nm SOI Device Technology von KleinOsowski, A.J., Cannon, E.H., Gordon, M.S., Heidel, D.F., Oldiges, P., Plettner, C., Rodbell, K.P., Rose, R.D., Tang, H.H.K.

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Strained Si CMOS (SS CMOS) technology: opportunities and challenges von Rim, K., Anderson, R., Boyd, D., Cardone, F., Chan, K., Chen, H., Christansen, S., Chu, J., Jenkins, K., Kanarsky, T., Koester, S., Lee, B.H., Lee, K., Mazzeo, V., Mocuta, A., Mocuta, D., Mooney, P.M., Oldiges, P., Ott, J., Ronsheim, P., Roy, R., Steegen, A., Yang, M., Zhu, H., Ieong, M., Wong, H.-S.P.

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Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design von Mukhopadhyay, S., Keunwoo Kim, Xinlin Wang, Frank, D.J., Oldiges, P., Ching-Te Chuang, Roy, K.

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Sub-25nm FinFET with advanced fin formation and short channel effect engineering von Yamashita, T., Basker, V. S., Standaert, T., Yeh, C-C, Yamamoto, T., Maitra, K., Lin, C-H, Faltermeier, J., Kanakasabapathy, S., Wang, M., Sunamura, H., Jagannathan, H., Reznicek, A., Schmitz, S., Inada, A., Wang, J., Adhikari, H., Berliner, N., Lee, K.-L, Kulkarni, P., Zhu, Y., Kumar, A., Bryant, A., Wu, S., Kanarsky, T., Cho, J., Mclellan, E., Holmes, S. J., Johnson, R. C., Levin, T., Demarest, J., Li, J., Oldiges, P., Arnold, J., Colburn, M., Hane, M., Mcherron, D., Paruchuri, V. K., Doris, B., Miller, R. J., Bu, H., Khare, M., O'Neill, J., Leobandung, E.

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Stacked devices for SEU immune design von Oldiges, P, Rodbell, K, Ning, T, Cai, J, Heidel, D, Tang, H, Wissel, L, Gordon, M

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Critical analysis of 14nm device options von Oldiges, P., Muralidhar, R., Kulkarni, P., Lin, C., Xiu, K., Guo, D., Bajaj, M., Sathaye, N.

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Theoretical determination of the temporal and spatial structure of alpha-particle induced electron-hole pair generation in silicon von Oldiges, P, Dennard, R, Heidel, D, Klaasen, B, Assaderaghi, F, Ieong, M

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Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications von Cheng, K., Khakifirooz, A., Kulkarni, P., Ponoth, S., Kuss, J., Shahrjerdi, D., Edge, L.F., Kimball, A., Kanakasabapathy, S., Xiu, K., Schmitz, S., Reznicek, A., Adam, T., He, H., Loubet, N., Holmes, S., Mehta, S., Yang, D., Upham, A., Seo, S.-C., Herman, J.L., Johnson, R., Zhu, Y., Jamison, P., Haran, B.S., Zhu, Z., Vanamurth, L.H., Fan, S., Horak, D., Bu, H., Oldiges, P.J., Sadana, D.K., Kozlowski, P., McHerron, D., O'Neill, J., Doris, B.

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Theoretical determination of the temporal and spatial structure of /spl alpha/-particle induced electron-hole pair generation in silicon von Oldiges, P., Dennard, R., Heidel, D., Klaasen, B., Assaderaghi, F., Ieong, M.

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Impact of Mobile Charge on Matching Sensitivity in SOI Analog Circuits von Connell, M., Grady, M., Oldiges, P., Onsongo, D., Passaro, M., Rausch, W., Ronsheim, P., Siljenberg, D.

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Protecting Big Blue from Rogue Subatomic Particles von Cannon, E.H., KleinOsowski, A., Gordon, M.S., Heidel, D.F., Hergenrother, J., Muller, K.P., Oldiges, P., Plettner, C., Reinhardt, D.D., Rodbell, K.P., Tang, H.H.K.

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Theoretical determination of the temporal and spatial structure of [alpha]-particle induced electron-hole pair generation in silicon von Oldiges, P, Dennard, R, Heidel, D, Klaasen, B, Assaderaghi, F, Ieong, M

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Technologies to further reduce soft error susceptibility in SOI von Oldiges, P., Dennard, R., Heidel, D., Ning, T., Rodbell, K., Tang, H., Gordon, M., Wissel, L.

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Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility von Frank, M.M., Paruchuri, V.K., Narayanan, V., Bojarczuk, N., Linder, B., Zafar, S., Cartier, E.A., Gusev, E.P., Jamison, P.C., Lee, K.L., Steen, M.L., Copel, M., Cohen, S.A., Maitra, K., Wang, X., Kozlowski, P.M., Newbury, J.S., Medeiros, D.R., Oldiges, P., Guha, S., Jammy, R., Ieong, M., Shahidi, G.

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