Efficient design and analysis of secure CMOS logic through logic encryption von Chandra, Sai Srinivas, Kannan, R. Jagadeesh, Balaji, B. Saravana, Veeramachaneni, Sreehari, Noor Mahammad, Sk

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An Approach to Place Sink Node in a Wireless Sensor Network (WSN) von Veeramani, S., Noor Mahammad, Sk

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Discrete Orthogonal Multi-transform on Chip (DOMoC) von M, Mohamed Asan Basiri, Sk, Noor Mahammad

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Fault tolerant micro-programmed control unit for SEU and MBU mitigation in space based digital systems von S., Deepanjali, Sk, Noor Mahammad

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Low power, high speed approximate multiplier for error resilient applications von S., Skandha Deepsita, Sk, Noor Mahammad

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Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor von Krishna, L. Hemanth, Sk, Ayesha, Rao, J. Bhaskara, Veeramachaneni, Sreehari, Sk, Noor Mahammad

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Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs von Sakali, Raghavendra Kumar, Veeramachaneni, Sreehari, Mahammad Sk, Noor

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High Precision and High Speed Handheld Scientific Calculator Design Using Hardware based CORDIC Algorithm von Kumar M., Shanmuga, Asan Basiri M., Mohamed, Mahammad Sk, Noor

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Configurable Folded IIR Filter Design von Basiri M, Mohamed Asan, Mahammad Sk, Noor

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A Perspective of IP Lookup Approach Using Graphical Processing Unit (GPU) von Sonai, Veeramani, Bharathi, Indira, Noor Mahammad, Sk

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Efficient Building Blocks for Reversible Sequential Circuit Design von Hari, Siva Kumar Sastry, Shroff, Shyam, Mahammad, Sk. Noor, Kamakoti, V.

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An efficient VLSI architecture for lifting based 1D/2D discrete wavelet transform von Asan Basiri M., Mohamed, Mahammad Sk, Noor

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Logically Optimal Novel 4:2 Compressor Architectures for High-Performance Applications von Priyadharshni, M., Chathalingathu, Anishchandran, Kumaravel, S., Manoharan, Arun, Veeramachaneni, Sreehari, Mahammad, Sk Noor

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Constructing Online Testable Circuits Using Reversible Logic von Mahammad, S.N., Veezhinathan, K.

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Multi-mode parallel and folded VLSI architectures for 1D-fast Fourier transform von Asan Basiri M, Mohamed, Mahammad Sk, Noor

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Efficient IP lookup using hybrid trie-based partitioning of TCAM-based open flow switches von Veeramani, S., Noor Mahammad, Sk

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Deterministic Approach for Range-enhanced Reconfigurable Packet Classification Engine von M, Dhayalakumar, Sk, Noor Mahammad

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Genetic annealing with efficient strategies to improve the performance for the NP-hard and routing problems von Eswarawaka, Rajesh, Noor Mahammad, S.K., Eswara Reddy, B.

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A Novel Rule Mapping on TCAM for Power Efficient Packet Classification von Vegesna, S. M. Srinivasavarma, Nara, Ashok Chakravarthy, Sk, Noor Mahammad

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Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications von S., Skandha Deepsita, Karthikeyan, T., Sk, Noor Mahammad

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