Fine Cone-shaped Bumps for Three-dimensional LSI Package—An Optimization of Thermocompression Bonding Process von Nemoto, Shunsuke, Lim, Ying Ying, Nakagawa, Hiroshi, Kikuchi, Katsuya, Aoyagi, Masahiro

Volltext

Sub-Micron-Accuracy Gold-to-Gold Interconnection Flip-Chip Bonding Approach for Electronics--Optics Heterogeneous Integration von Tung, Bui Thanh, Suzuki, Motohiro, Kato, Fumiki, Nemoto, Shunsuke, Watanabe, Naoki, Aoyagi, Masahiro

Volltext

15-µm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications von Tung, Bui Thanh, Kato, Fumiki, Watanabe, Naoya, Nemoto, Shunsuke, Kikuchi, Katsuya, Aoyagi, Masahiro

Volltext

Erratum: "Sub-Micron-Accuracy Gold-to-Gold Interconnection Flip-Chip Bonding Approach for Electronics--Optics Heterogeneous Integration" von Bui, Tung Thanh, Suzuki, Motohiro, Kato, Fumiki, Nemoto, Shunsuke, Watanabe, Naoya, Aoyagi, Masahiro

Volltext

Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits von Melamed, Samson, Watanabe, Naoya, Nemoto, Shunsuke, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro

Volltext

Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits von Melamed, Samson, Watanabe, Naoya, Nemoto, Shunsuke, Shimamoto, Haruo, Kikuchi, Katsuya, Aoyagi, Masahiro

Volltext

15- mu m-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications von Tung, Bui Thanh, Kato, Fumiki, Watanabe, Naoya, Nemoto, Shunsuke, Kikuchi, Katsuya, Aoyagi, Masahiro

Volltext

Developing an application for 3D IC chip stacking technology: How to shift from fundamental to practical technology von AOYAGI, Masahiro, IMURA, Fumito, KATO, Fumiki, KIKUCHI, Katsuya, WATANABE, Naoya, SUZUKI, Motohiro, NAKAGAWA, Hiroshi, OKADA, Yoshikuni, YOKOSHIMA, Tokihiko, YAMAJI, Yasuhiro, NEMOTO, Shunsuke, TUNG, Bui Thanh, SAMSON, Melamed

Volltext

Developing a leading practical application for 3D IC chip stacking technology: How to progress from fundamental technology to application technology von AOYAGI, Masahiro, IMURA, Fumito, KATO, Fumiki, KIKUCHI, Katsuya, WATANABE, Naoya, SUZUKI, Motohiro, NAKAGAWA, Hiroshi, OKADA, Yoshikuni, YOKOSHIMA, Tokihiko, YAMAJI, Yasuhiro, NEMOTO, Shunsuke, BUI, Tung Thanh, MELAMED, Samson

Volltext

New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking von Aoyagi, Masahiro, Watanabe, Naoya, Suzuki, Motohiro, Kikuchi, Katsuya, Nemoto, Shunsuke, Arima, Noriaki, Ishizuka, Misaki, Suzuki, Koji, Shiomi, Toshio

Volltext bestellen

Modified thermosonic flip-chip bonding based on electroplated Cu microbumps and concave pads for high-precision low-temperature assembly applications von Tung Thanh Bui, Suzuki, Motohiro, Kato, Fumiki, Watanabe, Naoya, Nemoto, Shunsuke, Kikuchi, Katsuya, Aoyagi, Masahiro

Volltext

Wide bus chip-to-chip interconnection technology using fine pitch bump joint array for 3D LSI chip stacking von Aoyagi, M., Imura, F., Nemoto, S., Watanabe, N., Kato, F., Kikuchi, K., Nakagawa, H., Hagimoto, M., Uchida, H., Matsumoto, Y.

Volltext bestellen

Flip chip bonding for STJ detector using 3D integration technique von Hatakeyama, Souki, Morita, Kohei, Nemoto, Shunsuke, Kikuchi, Katsuya, Nakagawa, Hiroshi, Aoyagi, Masahiro, Naruse, Masato, Myoren, Hiroaki, Taino, Tohru

Volltext

METHOD FOR MANUFACTURING PORUS ELECTRODE AND PORUS ELECTRODE von MIHASHI MASAHIKO, NEMOTO SHUNSUKE, YASAKA SHINICHI

Volltext bestellen

3 次元IC 積層実装技術の実用化への取り組み: 基盤技術から実用技術へどのようにしてステップアップするのか von 青柳, 昌宏, 居村, 史人, 加藤, 史樹, 菊地, 克弥, 渡辺, 直也, 鈴木, 基史, 仲川, 博, 岡田, 義邦, 横島, 時彦, 山地, 泰弘, 根本, 俊介, Thanh, TUNG Bui, Melamed, SAMSON

Volltext

Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging von Kikuchi, Katsuya, Kato, Fumiki, Nemoto, Shunsuke, Nakagawa, Hiroshi, Aoyagi, Masahiro, Yasu, Youtaro, Koshiji, Kohji

Volltext bestellen

Method of manufacturing semiconductor device and semiconductor device manufacturing apparatus von Aoyagi Masahiro, Kato Fumiki, Nemoto Shunsuke, Bui Thanh Tung, Suzuki Motohiro, Watanabe Naoya, Ma Lai Na

Volltext bestellen

Investigation of optimized high-density flip-chip interconnect design including micro Au bumps and underfill for ultrabroadband (DC-40GHz) applications von Yasu, Y., Kato, F., Kikuchi, K., Nemoto, S., Nakagawa, H., Koshiji, K., Aoyagi, M.

Volltext

Heterogeneous integration approach based on flip-chip bonding and misalignment self-correction elements for electronics-optics integration applications von Tung, Bui Thanh, Suzuki, Motohiro, Kato, Fumiki, Nemoto, Shunsuke, Aoyagi, Masahiro

Volltext

Method of Manufacturing Semiconductor Device and Semiconductor Device Manufacturing Apparatus von BUI THANH TUNG, SUZUKI MOTOHIRO, AOYAGI MASAHIRO, WATANABE NAOYA, KATO FUMIKI, NEMOTO SHUNSUKE, MA LAI NA

Volltext bestellen