A Novel Scan Architecture for Low Power Scan-Based Testing von Mojtabavi Naeini, Mahshid, Ooi, Chia Yee

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An integrated DFT solution for power reduction in scan test applications by low power gating scan cell von Naeini, Mahshid Mojtabavi, Dass, Sreedharan Baskara, Ooi, Chia Yee, Yoneda, Tomokazu, Inoue, Michiko

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The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology von Naeini, Mahshid, Dass, Sreedharan, Ooi, Chia

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A New Full-Adder Based on Majority Function and Standard Gates von Mahshid, M N, Keivan, N

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