Scalability of the Si1-xGex source/drain technology for the 45-nm technology node and beyond von ENEMAN, Geert, VERHEYEN, Peter, DE MEYER, Kristin, ROOYACKERS, Rita, NOURI, Faran, WASHINGTON, Lori, SCHREUTELKAMP, Robert, MOROZ, Victor, SMITH, Lee, DE KEERSGIETER, An, JURCZAK, Malgorzata

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pMOSFET with 200% mobility enhancement induced by multiple stressors von Washington, L., Nouri, F., Thirupapuliyur, S., Eneman, G., Verheyen, P., Moroz, V., Smith, L., Xiaopeng Xu, Kawaguchi, M., Huang, T., Ahmed, K., Balseanu, M., Li-Qun Xia, Meihua Shen, Yihwan Kim, Rooyackers, R., Kristin De Meyer, Schreutelkamp, R.

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Exploring the limits of stress-enhanced hole mobility von Smith, L., Moroz, V., Eneman, G., Verheyen, P., Nouri, F., Washington, L., Jurczak, M., Penzin, O., Pramanik, D., De Meyer, K.

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Physical Mechanism and Gate Insulator Material Dependence of Generation and Recovery of Negative-Bias Temperature Instability in p-MOSFETs von Varghese, D., Gupta, G., Lakkimsetti, L.M., Saha, D., Ahmed, K., Nouri, F., Mahapatra, S.

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Model to predict gate tunneling current of plasma oxynitrides von Kraus, P.A., Ahmed, K.Z., Olsen, C.S., Nouri, F.

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The evaluation of performance parameters of MOSFETs with alternative gate dielectrics von Ahmed, K.Z., Kraus, P.A., Olsen, C., Nouri, F.

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Physical models for predicting plasma nitrided Si-O-N gate dielectric properties from physical metrology von Kraus, P.A., Ahmed, K.Z., Olsen, C.S., Nouri, F.

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Observation of nitrogen-enhanced doping deactivation at the polysilicon-oxynitride interface of pMOSFETs with 12-Å gate dielectrics von Ahmed, K.Z, Kraus, P.A, Olsen, C, Hung, S, Nouri, F

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Study of Ni-Silicide Contacts to Si:C Source/Drain von Mertens, Sofie, Cho, Yonah, Nouri, Faran, Schreutelkamp, Robert, Kim, Yihwan, Verheyen, Peter, Steenbergen, Johnny, Vrancken, Christa, Bender, Hugo, Richard, Olivier, Van Daele, Benny, Vandervorst, Wilfried, Absil, Philip, Kubicek, Stefan, Demeurisse, Caroline, Tokei, Zsolt, Lauwers, Anne, Geenen, Luc

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METHOD OF SUPPRESSING ANOMALOUS INCREASES IN THE THRESHOLD VOLTAGE OF A SEMICONDUCTOR DEVICE von NOURI, FARAN

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Diode Analysis of Electrically Active Defects in Recessed SiGe Source/Drain Diodes von Simoen, Eddy R., Bargallo Gonzalez, Mireia, Eneman, Geert, Verheyen, Peter, Claeys, C. L., Benedetti, Antonio, Bender, Hugo, De Meyer, Krtistien, Schreutelkamp, Robert, Washington, Lori, Nouri, Faran

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Ultra-Shallow Junctions Formed by Co-Implantation and Sub-Melt Laser Annealing von Felch, Susan B., Falepin, Annelies, Severi, Simone, Augendre, Emmanuel, Noda, Taiji, Parihar, Vijay, Nouri, Faran, Hoffmann, Tom, Pawlak, Bartek, Eyben, Pierre, Vandervorst, Wilfried, Thirupapuliyur, Sunderraj, Schreutelkamp, Robert, Collart, Erik, Graoui, Houda

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Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices von ZHENG, TAMMY, NOURI, FARAN

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METHOD FOR ELIMINATING STRESS INDUCED DISLOCATION IN CMOS DEVICES von NOURI, FARAN, MANLEY, MARTIN

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Method for suppressing narrow width effects in CMOS technology von NOURI FARAN

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METHOD OF SUPPRESSING ANOMALOUS INCREASES IN THE THRESHOLD VOLTAGE OF A SEMICONDUCTOR DEVICE von NOURI, FARAN

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Method of manufacturing shallow source/drain junctions in a salicide process von NOURI FARAN

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METHOD FOR SUPPRESSING NARROW WIDTH EFFECTS IN CMOS TECHNOLOGY von NOURI, FARAN

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NMOS transistor devices and methods for fabricating same von CHO YONAH, NOURI FARAN, THIRUPAPULIYUR SUNDERRAJ

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NMOS transistor devices and methods for fabricating same von Thirupapuliyur, Sunderraj, Nouri, Faran, Cho, Yonah

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