Recent progress in analog memory-based accelerators for deep learning von Tsai, Hsinyu, Ambrogio, Stefano, Narayanan, Pritish, Shelby, Robert M, Burr, Geoffrey W

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Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators von Rasch, Malte J., Mackin, Charles, Le Gallo, Manuel, Chen, An, Fasoli, Andrea, Odermatt, Frédéric, Li, Ning, Nandakumar, S. R., Narayanan, Pritish, Tsai, Hsinyu, Burr, Geoffrey W., Sebastian, Abu, Narayanan, Vijay

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Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element von Burr, Geoffrey W., Shelby, Robert M., Sidler, Severin, di Nolfo, Carmelo, Junwoo Jang, Boybat, Irem, Shenoy, Rohit S., Narayanan, Pritish, Virwani, Kumar, Giacometti, Emanuele U., Kurdi, Bulent N., Hyunsang Hwang

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Access devices for 3D crosspoint memory von Burr, Geoffrey W., Shenoy, Rohit S., Virwani, Kumar, Narayanan, Pritish, Padilla, Alvaro, Kurdi, Bülent, Hwang, Hyunsang

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Neuromorphic computing using non-volatile memory von Burr, Geoffrey W., Shelby, Robert M., Sebastian, Abu, Kim, Sangbum, Kim, Seyoung, Sidler, Severin, Virwani, Kumar, Ishii, Masatoshi, Narayanan, Pritish, Fumarola, Alessandro, Sanches, Lucas L., Boybat, Irem, Le Gallo, Manuel, Moon, Kibong, Woo, Jiyoo, Hwang, Hyunsang, Leblebici, Yusuf

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Perspective on training fully connected networks with resistive memories: Device requirements for multiple conductances of varying significance von Cristiano, Giorgio, Giordano, Massimo, Ambrogio, Stefano, Romero, Louis P., Cheng, Christina, Narayanan, Pritish, Tsai, Hsinyu, Shelby, Robert M., Burr, Geoffrey W.

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Optimised weight programming for analogue memory-based deep neural networks von Mackin, Charles, Rasch, Malte J., Chen, An, Timcheck, Jonathan, Bruce, Robert L., Li, Ning, Narayanan, Pritish, Ambrogio, Stefano, Le Gallo, Manuel, Nandakumar, S. R., Fasoli, Andrea, Luquin, Jose, Friz, Alexander, Sebastian, Abu, Tsai, Hsinyu, Burr, Geoffrey W.

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Bidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part I: Al/Mo/Pr0.7Ca0.3MnO3 Material Improvements and Device Measurements von Moon, Kibong, Fumarola, Alessandro, Sidler, Severin, Jang, Junwoo, Narayanan, Pritish, Shelby, Robert M., Burr, Geoffrey W., Hwang, Hyunsang

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Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices von Spoon, Katie, Tsai, Hsinyu, Chen, An, Rasch, Malte J., Ambrogio, Stefano, Mackin, Charles, Fasoli, Andrea, Friz, Alexander M., Narayanan, Pritish, Stanisavljevic, Milos, Burr, Geoffrey W.

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MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays von Shenoy, Rohit S, Burr, Geoffrey W, Virwani, Kumar, Jackson, Bryan, Padilla, Alvaro, Narayanan, Pritish, Rettner, Charles T, Shelby, Robert M, Bethune, Donald S, Raman, Karthik V, BrightSky, Matthew, Joseph, Eric, Rice, Philip M, Topuria, Teya, Kellock, Andrew J, Kurdi, Bülent, Gopalakrishnan, Kailash

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Bidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part II: Impact of Al/Mo/Pr0.7Ca0.3MnO3 Device Characteristics on Neural Network Training Accuracy von Fumarola, Alessandro, Sidler, Severin, Moon, Kibong, Jang, Junwoo, Shelby, Robert M., Narayanan, Pritish, Leblebici, Yusuf, Hwang, Hyunsang, Burr, Geoffrey W.

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Exploring the Design Space for Crossbar Arrays Built With Mixed-Ionic-Electronic-Conduction (MIEC) Access Devices von Narayanan, Pritish, Burr, Geoffrey W., Shenoy, Rohit S., Stephens, Samantha, Virwani, Kumar, Padilla, Alvaro, Kurdi, Bulent N., Gopalakrishnan, Kailash

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Equivalent-accuracy accelerated neural-network training using analogue memory von Ambrogio, Stefano, Narayanan, Pritish, Tsai, Hsinyu, Shelby, Robert M., Boybat, Irem, di Nolfo, Carmelo, Sidler, Severin, Giordano, Massimo, Bodini, Martina, Farinha, Nathan C. P., Killeen, Benjamin, Cheng, Christina, Jaoudi, Yassine, Burr, Geoffrey W.

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Noise-Resilient DNN: Tolerating Noise in PCM-Based AI Accelerators via Noise-Aware Training von Kariyappa, Sanjay, Tsai, Hsinyu, Spoon, Katie, Ambrogio, Stefano, Narayanan, Pritish, Mackin, Charles, Chen, An, Qureshi, Moinuddin, Burr, Geoffrey W.

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A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh von Jain, Shubham, Tsai, Hsinyu, Chen, Ching-Tzu, Muralidhar, Ramachandran, Boybat, Irem, Frank, Martin M., Wozniak, Stanislaw, Stanisavljevic, Milos, Adusumilli, Praneet, Narayanan, Pritish, Hosokawa, Kohji, Ishii, Masatoshi, Kumar, Arvind, Narayanan, Vijay, Burr, Geoffrey W.

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Weight Programming in DNN Analog Hardware Accelerators in the Presence of NVM Variability von Mackin, Charles, Tsai, Hsinyu, Ambrogio, Stefano, Narayanan, Pritish, Chen, An, Burr, Geoffrey W.

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Analog-to-Digital Conversion With Reconfigurable Function Mapping for Neural Networks Activation Function Acceleration von Giordano, Massimo, Cristiano, Giorgio, Ishibashi, Koji, Ambrogio, Stefano, Tsai, Hsinyu, Burr, Geoffrey W., Narayanan, Pritish

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Fabrication of Microsensor for Detection of Low-Concentration Formaldehyde Gas in Formalin-Treated Fish von Ghione, Giovanni, Xu, Nuo, Kuroda, Rihito, Alam, Syed M., Narayanan, Pritish, Thadesar, Paragkumar A., Phillips, Jamie, Conley, John F., Park, Jin-Seong, Graham, Samuel, Letizia, Rosa

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Training fully connected networks with resistive memories: impact of device failures von Romero, Louis P, Ambrogio, Stefano, Giordano, Massimo, Cristiano, Giorgio, Bodini, Martina, Narayanan, Pritish, Tsai, Hsinyu, Shelby, Robert M, Burr, Geoffrey W

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Introduction to JPDC special issue on computing with future nanotechnology von Moritz, Csaba Andras, Khasanvis, Santosh, Narayanan, Pritish

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