Replication-Based Load Balancing von Nahir, Amir, Orda, Ariel, Raz, Danny

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Topology Design of Communication Networks: A Game-Theoretic Perspective von Nahir, Amir, Orda, Ariel, Freund, Ari

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Workload Factoring: A Game-Theoretic Perspective von Nahir, Amir, Orda, Ariel, Raz, Danny

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Hardware and Software: Verification and Testing : 8th International Haifa Verification Conference, HVC 2012, Haifa, Israel, November 6-8, 2012. Revised Selected Papers von Biere, Armin, Nahir, Amir, Vos, Tanja E.J

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Automated Reencoding of Boolean Formulas von Manthey, Norbert, Heule, Marijn J. H., Biere, Armin

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Scheduling-based test-case generation for verification of multimedia SoCs von Nahir, Amir, Ziv, Avi, Emek, Roy, Keidar, Tal, Ronen, Nir

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Word Equations with Length Constraints: What's Decidable? von Ganesh, Vijay, Minnes, Mia, Solar-Lezama, Armando, Rinard, Martin

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Hardware and Software: 8th International Haifa Verification Conference, HVC 2012, Haifa, Israel, November 6-8, 2012. Revised Selected Papers von Biere, Armin, Nahir, Amir, Vos, Tanja

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Functional verification of power gated designs by compositional reasoning von Eisner, Cindy, Nahir, Amir, Yorav, Karen

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Threadmill: a post-silicon exerciser for multi-threaded processors von Adir, Allon, Golubev, Maxim, Landa, Shimon, Nahir, Amir, Shurek, Gil, Sokhin, Vitali, Ziv, Avi

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Computing Interpolants without Proofs von Chockler, Hana, Ivrii, Alexander, Matsliah, Arie

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FoREnSiC – An Automatic Debugging Environment for C Programs von Bloem, Roderick, Drechsler, Rolf, Fey, Görschwin, Finder, Alexander, Hofferek, Georg, Könighofer, Robert, Raik, Jaan, Repinski, Urmas, Sülflow, André

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Topology Design and Control: A Game-Theoretic Perspective von Nahir, A., Orda, A., Freund, A.

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Repair with On-The-Fly Program Analysis von Könighofer, Robert, Bloem, Roderick

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TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead von de Paula, Flavio M., Nahir, Amir, Nevo, Ziv, Orni, Avigail, Hu, Alan J.

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Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor von Adir, Allon, Nahir, Amir, Shurek, Gil, Ziv, Avi, Meissner, Charles, Schumann, John

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Deterministic Compilation of Temporal Safety Properties in Explicit State Model Checking von Rozier, Kristin Yvonne, Vardi, Moshe Y.

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Emulation in post-silicon validation: It's not just for functionality anymore von Balston, K., Hu, A. J., Wilton, S. J. E., Nahir, A.

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Test Case Generation by Grammar-Based Fuzzing for Model-Driven Engineering von Widl, Magdalena

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Coverage-Based Trace Signal Selection for Fault Localisation in Post-silicon Validation von Zhu, Charlie Shucheng, Weissenbacher, Georg, Malik, Sharad

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