Neurons With Captive Synaptic Devices for Temperature Robust Spiking Neural Networks von Park, Kyungchul, Kim, Sungjoon, Baek, Myung-Hyun, Jeon, Bosung, Kim, Yeon-Woo, Choi, Woo Young

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System-Level Simulation of Hardware Spiking Neural Network Based on Synaptic Transistors and I&F Neuron Circuits von Hwang, Sungmin, Kim, Hyungjin, Park, Jungjin, Kwon, Min-Woo, Baek, Myung-Hyun, Lee, Jeong-Jun, Park, Byung-Gook

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Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation von Kwon, Min-Woo, Baek, Myung-Hyun, Hwang, Sungmin, Park, Kyungchul, Jang, Tejin, Kim, Taehyung, Lee, Junil, Cho, Seongjae, Park, Byung-Gook

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Polysilicon-Channel Synaptic Transistors for Implementation of Short- and Long-Term Memory Characteristics von Baek, Myung-Hyun, Kim, Hyungjin

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A Low-Energy High-Density Capacitor-Less I&F Neuron Circuit Using Feedback FET Co-Integrated With CMOS von Kwon, Min-Woo, Park, Kyungchul, Baek, Myung-Hyun, Lee, Junil, Park, Byung-Gook

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A Novel Vector-matrix Multiplication (VMM) Architecture based on NAND Memory Array von Kim, Suhyeon, Baek, Myung-Hyun, Hwang, Sungmin, Jang, Taejin, Park, Kyungchul, Park, Byung-Gook

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Grain boundary induced short-term memory effect in fully depleted thin-polysilicon devices von Baek, Myung-Hyun, Jang, Taejin, Kim, Hyungjin, Park, Jungjin, Kwon, Min-Woo, Hwang, Sungmin, Kim, Suhyeon, Lee, Jeong-Jun, Park, Byung-Gook

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Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation von Kwon, Dae Woong, Kim, Wandong, Kim, Do-Bin, Lee, Sang-Ho, Seo, Joo Yun, Baek, Myung-Hyun, Park, Ji-Ho, Choi, Eunseok, Cho, Gyu Seong, Park, Sung-Kye, Lee, Jong-Ho, Park, Byung-Gook

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Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation von Song, Seunghwan, Jeon, Bosung, Hwang, Sungmin, Baek, Myung-Hyun, Lee, Jong-Ho, Park, Byung-Gook

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Design and Characterization of Semi-Floating-Gate Synaptic Transistor von Cho, Yongbeom, Lee, Jae Yoon, Yu, Eunseon, Han, Jae-Hee, Baek, Myung-Hyun, Cho, Seongjae, Park, Byung-Gook

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CMOS Analog Integrate-and-fire Neuron Circuit for Driving Memristor based on RRAM von Min-Woo Kwon, Myung-Hyun Baek, Jungjin Park, Hyungjin Kim, Sungmin Hwang, Byung-Gook Park

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Input-modulating adaptive neuron circuit employing asymmetric floating-gate MOSFET with two independent control gates von Kim, Taehyung, Park, Kyungchul, Jang, Taejin, Baek, Myung-Hyun, Song, Young Suh, Park, Byung-Gook

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Implementation of Neuromorphic System with Si-based Floating-body Synaptic Transistors von Jungjin Park, Hyungjin Kim, Min-Woo Kwon, Sungmin Hwang, Myung-Hyun Baek, Jeong-Jun Lee, Taejin Jang, Byung-Gook Park

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Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory von Myung-Hyun Baek, Do-Bin Kim, Seunghyun Kim, Sang-Ho Lee, Byung-Gook Park

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Tunneling oxide engineering for improving retention in nonvolatile charge-trapping memory with TaN/Al2O3/HfO2/SiO2/Al2O3/SiO2/Si structure von Song, Young Suh, Jang, Taejin, Min, Kyung Kyu, Baek, Myung-Hyun, Yu, Junsu, Kim, Yeonwoo, Lee, Jong-Ho, Park, Byung-Gook

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Investigation of transient current characteristics with scaling-down poly-Si body thickness and grain size of 3D NAND flash memory von Lee, Sang-Ho, Kwon, Dae Woong, Kim, Seunghyun, Baek, Myung-Hyun, Lee, Sungbok, Kang, Jinkyu, Jang, Woojae, Park, Byung-Gook

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Comparison of writing methods of single memory cell with volatile and nonvolatile memory functions von Kim, Hyungjin, Baek, Myung-Hyun, Hwang, Sungmin, Lee, Jong-Ho, Park, Byung-Gook

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Layer Selection by Multi-Level Permutation in 3-D Stacked NAND Flash Memory von Lee, Sang-Ho, Kim, Wandong, Kwon, Dae Woong, Seo, Joo Yun, Baek, Myung Hyun, Lee, Sungbok, Kang, Jinkyu, Jang, Woojae, Lee, Jong-Ho, Park, Byung-Gook

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Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory von Kwon, Dae Woong, Kim, Wandong, Kim, Do-Bin, Lee, Sang-Ho, Seo, Joo Yun, Baek, Myung Hyun, Park, Ji-Ho, Choi, Eunseok, Cho, Gyu Seong, Park, Sung-Kye, Park, Byung-Gook

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Tunneling oxide engineering for improving retention in nonvolatile charge-trapping memory with TaN/Al 2 O 3 /HfO 2 /SiO 2 /Al 2 O 3 /SiO 2 /Si structure von Song, Young Suh, Jang, Taejin, Min, Kyung Kyu, Baek, Myung-Hyun, Yu, Junsu, Kim, Yeonwoo, Lee, Jong-Ho, Park, Byung-Gook

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