Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration von Nag, Anirban, Balasubramonian, Rajeev, Srikumar, Vivek, Walker, Ross, Shafiee, Ali, Strachan, John Paul, Muralimanohar, Naveen

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Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories von Yoon, Hanbin, Meza, Justin, Muralimanohar, Naveen, Jouppi, Norman P., Mutlu, Onur

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Understanding the trade-offs in multi-level cell ReRAM memory design von Xu, Cong, Niu, Dimin, Muralimanohar, Naveen, Jouppi, Norman P., Xie, Yuan

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CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models von Jouppi, Norman P., Kahng, Andrew B., Muralimanohar, Naveen, Srinivas, Vaishnav

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Interconnect design considerations for large NUCA caches von Muralimanohar, Naveen, Balasubramonian, Rajeev

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Architecting Efficient Interconnects for Large Caches with CACTI 6.0 von Muralimanohar, N., Balasubramonian, R., Jouppi, N.P.

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Near-Memory Data Services von Falsafi, Babak, Stan, Mircea, Skadron, Kevin, Jayasena, Nuwan, Chen, Yunji, Tao, Jinhua, Nair, Ravi, Moreno, Jaime, Muralimanohar, Naveen, Sankaralingam, Karthikeyan, Estan, Cristian

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LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems von Udipi, A. N., Muralimanohar, N., Balsubramonian, R., Davis, A., Jouppi, N. P.

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The role of optics in future high radix switch design von Binkert, Nathan, Davis, Al, Jouppi, Norman P., McLaren, Moray, Muralimanohar, Naveen, Schreiber, Robert, Ahn, Jung Ho

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Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems von Udipi, Aniruddha N., Muralimanohar, Naveen, Balasubramonian, Rajeev, Davis, Al, Jouppi, Norman P.

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Optical high radix switch design von Binkert, N., Davis, A., Jouppi, N., McLaren, M., Muralimanohar, N., Schreiber, R., Ahn, J. H.

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Staged Reads: Mitigating the impact of DRAM writes on DRAM reads von Chatterjee, N., Muralimanohar, N., Balasubramonian, R., Davis, A., Jouppi, N. P.

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Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism von Doe Hyun Yoon, Muralimanohar, N., Jichuan Chang, Ranganathan, P., Jouppi, Norman P., Erez, M.

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Interconnect-Aware Coherence Protocols for Chip Multiprocessors von Cheng, Liqun, Muralimanohar, Naveen, Ramani, Karthik, Balasubramonian, Rajeev, Carter, John B.

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Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy von Madan, N., Li Zhao, Muralimanohar, N., Udipi, A., Balasubramonian, R., Iyer, R., Makineni, S., Newell, D.

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Hierarchical computations on sparse matrix rows via a memristor array von Muralimanohar, Naveen

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MEMRISTIVE DOT PRODUCT CIRCUIT BASED FLOATING POINT COMPUTATIONS von MURALIMANOHAR, Naveen, FEINBERG, Benjamin

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Processing in-memory architectures for performing logical operations von Shafiee Ardestani, Ali, Muralimanohar, Naveen

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Data processing using resistive memory arrays von Shafiee Ardestani, Ali, Muralimanohar, Naveen

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Draining a write queue based on information from a read queue von Muralimanohar, Naveen, Balasubramonian, Rajeev

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