Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking von Kurd, N., Mosalikanti, P., Neidengard, M., Douglas, J., Kumar, R.

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Next Generation IntelA= Coreac Micro-Architecture (Nehalem) Clocking von Kurd, N, Mosalikanti, P, Neidengard, M, Douglas, J, Kumar, R

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Next generation Intel® micro-architecture (Nehalem) clocking architecture von Kurd, N., Douglas, J., Mosalikanti, P., Kumar, R.

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High performance DDR architecture in Intel® Core™ processors using 32nm CMOS high-K metal-gate process von Mosalikanti, P, Mozak, C, Kurd, N

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Haswell: A Family of IA 22 nm Processors von Kurd, Nasser, Chowdhury, Muntaquim, Burton, Edward, Thomas, Thomas P., Mozak, Christopher, Boswell, Brent, Mosalikanti, Praveen, Neidengard, Mark, Deval, Anant, Khanna, Ashish, Chowdhury, Nasirul, Rajwar, Ravi, Wilson, Timothy M., Kumar, Rajesh

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METHODS AND APPARATUSES FOR DELAY-LOCKED LOOPS AND PHASE-LOCKED LOOPS von MOZAK, CHRISTOPHER P, MOSALIKANTI, PRAVEEN, KURD, NASSER A

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METHODS AND APPARATUSES FOR DELAY-LOCKED LOOPS AND PHASE-LOCKED LOOPS von MOZAK, CHRISTOPHER P, MOSALIKANTI, PRAVEEN, KURD, NASSER A

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Methods and apparatuses for delay-locked loops and phase-locked loops von Mosalikanti, Praveen, Kurd, Nasser A, Mozak, Christopher P

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Methods and apparatuses for delay-locked loops and phase-locked loops von MOSALIKANTI PRAVEEN, KURD NASSER A, MOZAK CHRISTOPHER P

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METHODS AND APPARATUSES FOR DELAY-LOCKED LOOPS AND PHASE-LOCKED LOOPS von MOZAK, CHRISTOPHER P, MOSALIKANTI, PRAVEEN, KURD, NASSER A

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METHODS AND APPARATUSES FOR DELAY-LOCKED LOOPS AND PHASE-LOCKED LOOPS von MOZAK, CHRISTOPHER P, MOSALIKANTI, PRAVEEN, KURD, NASSER A

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Methods and Apparatuses for Delay-Locked Loops and Phase-Locked Loops von MOSALIKANTI PRAVEEN, KURD NASSER A, MOZAK CHRISTOPHER P

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METHOD AND APPARATUS FOR DELAY-LOCKED LOOP AND PHASE-LOCKED LOOP von PRAVEEN MOSALIKANTI, NASSER A KURD, MOZAK CHRISTOPHER P

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Fuse cell array with redundancy features von Chen, Zhanping, Douglas, Jonathan P, Mosalikanti, Praveen, Zhang, Kevin, Taylor, Gregory F

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Fuse cell array with redundancy features von DOUGLAS JONATHAN P, MOSALIKANTI PRAVEEN, ZHANG KEVIN, TAYLOR GREGORY F, CHEN ZHANPING

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METHODS AND APPARATUSES FOR DELAY-LOCKED LOOPS AND PHASE-LOCKED LOOPS von MOSALIKANTI PRAVEEN, KURD NASSER A, MOZAK CHRISTOPHER P

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Fuse cell array with redundancy features von DOUGLAS JONATHAN P, MOSALIKANTI PRAVEEN, ZHANG KEVIN, TAYLOR GREGORY F, CHEN ZHANPING

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Shared sense amplifier for fuse cell von DOUGLAS JONATHAN P, MOSALIKANTI PRAVEEN, ZHANG KEVIN, TAYLOR GREGORY F, CHEN ZHANPING

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