LAXY: A Location-Based Aging-Resilient Xy-Yx Routing Algorithm for Network on Chip von Rohbani, Nezam, Shirmohammadi, Zahra, Zare, Maryam, Miremadi, Seyed-Ghassem

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A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction von Farbeh, Hamed, Mirzadeh, Nooshin Sadat, Ghalaty, Nahid Farhady, Miremadi, Seyed-Ghassem, Fazeli, Mahdi, Asadi, Hossein

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A Low Area Overhead NBTI/PBTI Sensor for SRAM Memories von Karimi, Maryam, Rohbani, Nezam, Miremadi, Seyed-Ghassem

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An efficient numerical-based crosstalk avoidance codec design for NoCs von Shirmohammadi, Zahra, Mozafari, Fereshte, Miremadi, Seyed-Ghassem

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Bias Temperature Instability Mitigation via Adaptive Cache Size Management von Rohbani, Nezam, Ebrahimi, Mojtaba, Miremadi, Seyed-Ghassem, Tahoori, Mehdi B.

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A fast, flexible, and easy-to-develop FPGA-based fault injection technique von Ebrahimi, Mojtaba, Mohammadi, Abbas, Ejlali, Alireza, Miremadi, Seyed Ghassem

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A low-overhead and reliable switch architecture for Network-on-Chips von Patooghy, Ahmad, Ghassem Miremadi, Seyed, Fazeli, Mahdi

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Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems von Ebrahimi, Mojtaba, Miremadi, Seyed Ghassem, Asadi, Hossein, Fazeli, Mahdi

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Efficient algorithms to accurately compute derating factors of digital circuits von Asadi, Hossein, Tahoori, Mehdi B., Fazeli, Mahdi, Miremadi, Seyed Ghassem

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Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates von Rezaei, Siavash, Miremadi, Seyed Ghassem, Asadi, Hossein, Fazeli, Mahdi

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Operand Width Aware Hardware Reuse: A low cost fault-tolerant approach to ALU design in embedded processors von Fazeli, Mahdi, Namazi, Alireza, Miremadi, Seyed-Ghassem, Haghdoost, Alireza

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Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks von Ejlali, A., Al-Hashimi, B.M., Rosinger, P., Miremadi, S.G., Benini, L.

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Complement routing: A methodology to design reliable routing algorithm for Network on Chips von Patooghy, Ahmad, Miremadi, Seyed Ghassem

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FPGA-based Monte Carlo simulation for fault tree analysis von Ejlali, Alireza, Ghassem Miremadi, Seyed

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Error propagation analysis using FPGA-based SEU-fault injection von Ejlali, Alireza, Miremadi, Seyed Ghassem

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Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems von Ejlali, A., Al-Hashimi, B.M., Schmitz, M.T., Rosinger, P., Miremadi, S.G.

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TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches von Cheshmikhani, Elham, Farbeh, Hamed, Miremadi, Seyed Ghassem, Asadi, Hossein

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LEXACT: Low Energy N-Modular Redundancy Using Approximate Computing for Real-Time Multicore Processors von Baharvand, Farshad, Miremadi, Seyed Ghassem

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CFCET: A hardware-based control flow checking technique in COTS processors using execution tracing von Rajabzadeh, Amir, Miremadi, Seyed Ghassem

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Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches von Farbeh, Hamed, Kim, Hyeonggyu, Miremadi, Seyed Ghassem, Kim, Soontae

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