A Predictive Approach for Conditional Execution of Memristive Material Implication Stateful Logic Operations von Dias, Cesar de S., Marranghello, Felipe S., Brum, Raphael Martins, Butzen, Paulo F.

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maj-[Formula Omitted] Logic Synthesis for Emerging Technology von Neutzling, Augusto, Marranghello, Felipe S, Matos, Jody Maick, Reis, Andre, Ribas, Renato P

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SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC von Dal Bem, Vinicius, Marranghello, Felipe S., Reis, Andre I., Ribas, Renato P.

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Impact and optimization of lithography-aware regular layout in digital circuit design von Dal Bem, V., Butzen, P., Marranghello, F. S., Reis, A. I., Ribas, R. P.

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Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization von Amaru, Luca Gaetano, Testa, Eleonora, Vuillod, Patrick, Luo, Jiong, Neves Possani, Vinicius, dos Santos Marranghello, Felipe, Casares, Christopher

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CMOS inverter delay model based on DC transfer curve for slow input von Marranghello, F. S., Reis, A. I., Ribas, R. P.

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Design-oriented delay model for CMOS inverter von Marranghello, F. S., Reis, A. I., Ribas, R. P.

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Exact Benchmark Circuits for Logic Synthesis von Neto, Walter Lau, Possani, Vinicius N., Marranghello, Felipe S., Matos, Jody Maick, Gaillardon, Pierre-Emmanuel, Reis, Andre Inacio, Ribas, Renato Perez

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SAT-Sweeping Enhanced for Logic Synthesis von Amaru, Luca, Marranghello, Felipe, Testa, Eleonora, Casares, Christopher, Possani, Vinicius, Luo, Jiong, Vuillod, Patrick, Mishchenko, Alan, De Micheli, Giovanni

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