Fixed-outline floorplanning: enabling hierarchical design von Adya, S.N., Markov, I.L.

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A layered software architecture for quantum computing design tools von Svore, K.M., Aho, A.V., Cross, A.W., Chuang, I., Markov, I.L.

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Min-cut floorplacement von Roy, J.A., Adya, S.N., Papa, D.A., Markov, I.L.

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Ending Piracy of Integrated Circuits von Roy, J A, Koushanfar, F, Markov, I L

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Error-correction and crosstalk avoidance in DSM busses von Patel, K.N., Markov, I.L.

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SimPL: An Effective Placement Algorithm von Myung-Chul Kim, Dong-Jin Lee, Markov, I. L.

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Watermarking techniques for intellectual property protection von Kahng, A B, Lach, J, Mangione-Smith, W H, Mantik, S, Markov, I L, Potkonjak, M, Tucker, P, Wang, H, Wolfe, G

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Breaking Instance-Independent Symmetries In Exact Graph Coloring von Ramani, A., Markov, I. L., Sakallah, K. A., Aloul, F. A.

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Simulation-Based Bug Trace Minimization With BMC-Based Refinement von Kai-Hui Chang, Bertacco, V., Markov, I.L.

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Solution and Optimization of Systems of Pseudo-Boolean Constraints von Aloul, F.A., Ramani, A., Sakallah, K.A., Markov, I.L.

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Assembling 2-D Blocks Into 3-D Chips von Knechtel, Johann, Markov, I. L., Lienig, J.

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On wirelength estimations for row-based placement von Caldwell, A.E., Kahng, A.B., Mantik, S., Markov, I.L., Zelikovsky, A.

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ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement von Kim, Myung-Chul, Markov, Igor L.

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Progress and challenges in VLSI placement research von Markov, Igor L., Hu, Jin, Kim, Myung-Chul

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Sensitivity-guided metaheuristics for accurate discrete gate sizing von Hu, Jin, Kahng, Andrew B., Kang, SeokHyeong, Kim, Myung-Chul, Markov, Igor L.

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Improved a priori interconnect predictions and technology extrapolation in the GTX system von Yu Cao, Chenming Hu, Xuejue Huang, Kahng, A.B., Markov, I.L., Oliver, M., Stroobandt, D., Sylvester, D.

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SimPL: An effective placement algorithm von Myung-Chul Kim, Dong-Jin Lee, Markov, I L

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Design and implementation of the Fiduccia-Mattheyses heuristic for VLSI netlist partitioning von CALDWELL, A. E, KAHNG, A. B, MARKOV, I. L

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Signature-Based SER Analysis and Design of Logic Circuits von Krishnaswamy, S., Plaza, S.M., Markov, I.L., Hayes, J.P.

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Multiobjective optimization of deadspace, a critical resource for 3D-IC integration von Knechtel, Johann, Markov, Igor L., Lienig, Jens, Thiele, Matthias

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