Kobold: Simplified Cache Coherence for Cache-Attached Accelerators von Brana, Jennifer, Schwedock, Brian C., Manerkar, Yatin A., Beckmann, Nathan

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Full-Stack Memory Model Verification with TriCheck von Trippel, Caroline, Manerkar, Yatin A., Lustig, Daniel, Pellauer, Michael, Martonosi, Margaret

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Modelling and Verification of Security-Oriented Resource Partitioning Schemes von Godbole, Adwait, Ye, Leiqi, Manerkar, Yatin A., Seshia, Sanjit A.

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Towards Building Verifiable CPS using Lingua Franca von Lin, Shaokai, Manerkar, Yatin A., Lohstroh, Marten, Polgreen, Elizabeth, Yu, Sheng-Jung, Jerad, Chadlia, Lee, Edward A., Seshia, Sanjit A.

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TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA von Trippel, Caroline, Manerkar, Yatin A., Lustig, Daniel, Pellauer, Michael, Martonosi, Margaret

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SemPat: Using Hyperproperty-based Semantic Analysis to Generate Microarchitectural Attack Patterns von Godbole, Adwait, Manerkar, Yatin A, Seshia, Sanjit A

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Automated Conversion of Axiomatic to Operational Models: Theory and Practice von Godbole, Adwait, Manerkar, Yatin A, Seshia, Sanjit A

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RealityCheck: Bringing Modularity, Hierarchy, and Abstraction to Automated Microarchitectural Memory Consistency Verification von Manerkar, Yatin A, Lustig, Daniel, Martonosi, Margaret

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SemPat: Using Hyperproperty-based Semantic Analysis to Generate Microarchitectural Attack Patterns von Godbole, Adwait, Manerkar, Yatin A, Seshia, Sanjit A

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UCLID5: Multi-Modal Formal Modeling, Verification, and Synthesis von Polgreen, Elizabeth, Cheang, Kevin, Gaddamadugu, Pranav, Godbole, Adwait, Laeufer, Kevin, Lin, Shaokai, Manerkar, Yatin A, Mora, Federico, Seshia, Sanjit A

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Automated Conversion of Axiomatic to Operational Models: Theory and Practice von Godbole, Adwait, Manerkar, Yatin A, Seshia, Sanjit A

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RealityCheck: Bringing Modularity, Hierarchy, and Abstraction to Automated Microarchitectural Memory Consistency Verification von Manerkar, Yatin A, Lustig, Daniel, Martonosi, Margaret

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TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA von Trippel, Caroline, Manerkar, Yatin A., Lustig, Daniel, Pellauer, Michael, Martonosi, Margaret

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UCLID5: Multi-Modal Formal Modeling, Verification, and Synthesis von Polgreen, Elizabeth, Cheang, Kevin, Gaddamadugu, Pranav, Godbole, Adwait, Laeufer, Kevin, Lin, Shaokai, Manerkar, Yatin A, Mora, Federico, Seshia, Sanjit A

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TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA von Trippel, Caroline, Manerkar, Yatin A., Lustig, Daniel, Pellauer, Michael, Martonosi, Margaret

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TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA von Trippel, Caroline, Manerkar, Yatin A, Lustig, Daniel, Pellauer, Michael, Martonosi, Margaret

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Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings von Manerkar, Yatin A, Trippel, Caroline, Lustig, Daniel, Pellauer, Michael, Martonosi, Margaret

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Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings von Manerkar, Yatin A, Trippel, Caroline, Lustig, Daniel, Pellauer, Michael, Martonosi, Margaret

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