Design-for-test methodologies for current tests in Analog/Mixed-Signal Power SOCs von Kulovic, Kemal, Maltabas, S., Margala, M.

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An IDDQ BIST approach to characterize phase-locked loop parameters von Maltabas, S., Ekekon, O. K., Kulovic, K., Meixner, A., Margala, M.

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Novel programmable built-in current-sensor for analog, digital and mixed-signal circuits von Ekekon, O K, Maltabas, S, Margala, M

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A multi-GHz PLL Built-In jitter extraction circuit for deep submicron technologies von Ekekon, O. K., Maltabas, S., Margala, M.

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Novel Practical Built-in Current Sensors von Maltabas, Samed, Kulovic, Kemal, Margala, Martin

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Reconfigurable clock flipping scheme for duty cycle measurement von Alashmouny, Khaled M, Maltabas, Samed, Fischette, Jr., Dennis M

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Reference clock switching in phase-locked loop circuits von Liu, Shaobo, Park, Pyoungwon, Ang, Boon-Aik, Chen, Yu, Santos, Gregory N, Chiang, Meei-Ling, Maltabas, Samed, Fischette, Jr., Dennis M, Sajnani, Litesh, Yu, Hairong, Su, Richard Y

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Hybrid asynchronous gray counter with non-gray zone detector for high performance phase-locked loops von Liu, Shaobo, Zhang, Dabin, Chen, Yu, Chiang, Meei-Ling, Maltabas, Samed, Fischette, Jr., Dennis M

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Reference Clock Switching in Phase-Locked Loop Circuits von Liu, Shaobo, Park, Pyoungwon, Ang, Boon-Aik, Chen, Yu, Santos, Gregory N, Chiang, Meei-Ling, Maltabas, Samed, Sajnani, Litesh, Fischette, JR., Dennis M, Yu, Hairong, Su, Richard Y

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A new built-in IDDQ testing method using programmable BICS von Maltabas, Samed, Ekekon, Osman Kubilay, Margala, Martin

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Adaptively reconfigurable time-to-digital converter for digital phase-locked loops von Chiang, Meei-Ling, Deng, Wei, Maltabas, Samed, Fischette, Jr., Dennis M

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Power minimization methodology for VCTL topologies von Ekekon, Osman Kubilay, Maltabas, Samed, Margala, Martin, Cilingiroglu, Ugur

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